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| Datasheet File OCR Text: |
| this is information on a product in full production. september 2013 doc id 023553 rev 3 1/128 1 L99PM72PXP advanced power management syst em ic with embedded lin and high speed can transceiver su pporting can partial networking datasheet ? production data features two 5 v voltage regulators for microcontroller and peripheral supply no electrolytic capacitor required on regulator outputs ultra low quiescent curr ent in standby modes programmable reset generator for power-on and undervoltage configurable window wa tchdog and fail safe output lin 2.1 compliant ( saej2602 compatible) transceiver advanced high speed can transceiver (iso 11898-2/-5 and sae j22 84 compliant) with local failure and bus failure diagnosis and selective wake-up functionality according to iso 11898-6 complete 3 channel contact monitoring interface with progra mmable cyclic sense functionality programmable periodi c system wake-up feature st spi interface for mode control and diagnosis 5 fully protected high-side drivers with internal 4-channel pwm generator 2 low-side drivers with active zener clamping 4 internal pwm timers 2 operational amplifiers with rail-to-rail outputs (v s ) and low voltage inputs temperature warning and thermal shutdown applications automotive ecu's such as door zone and body control modules description description the L99PM72PXP is a power management system ic providing electronic control units with enhanced system power supply functionality including various standby modes as well as lin and hs can physical communication layers. it contains two low drop voltage regulators to supply the system microcontroller and external peripheral loads such as sensors and provides enhanced system standby functionality with programmable local and remote wake up capability. in addition, five high-side drivers, two low-side drivers and two operational amplifiers increase the system integration level. the st standard spi interface (3.0) allows control and diagnosis of the device and enables generic software development. * $ 3 * & ) 7 powersso-36 table 1. device summary package order code tube tape and reel powersso-36 L99PM72PXP L99PM72PXPtr www.st.com
contents L99PM72PXP 2/128 doc id 023553 rev 3 contents 1 block diagram and pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 2 detailed description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 2.1 voltage regulators . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 2.1.1 voltage regulator: v 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 2.1.2 voltage regulator: v 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 2.1.3 increased ou tput current capability for voltage regulator v 2 . . . . . . . . . 14 2.1.4 voltage regulator failure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 2.1.5 voltage regulator behavior . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 2.2 operating modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 2.2.1 active mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 2.2.2 flash mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 2.2.3 sw-debug mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 2.2.4 v 1_standby mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 2.2.5 interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 2.2.6 v bat_standby mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 2.2.7 wake up from standby modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 2.2.8 wake up inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 2.2.9 cyclic contact supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 2.2.10 timer interrupt / wake-up of microcontroller by timer . . . . . . . . . . . . . . . 22 2.3 functional overview (truth table) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 2.4 configurable window watchdog . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 2.4.1 change watchdog timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 2.5 fail safe mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 2.5.1 single failures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 2.5.2 multiple failures ? entering forced v bat_standby mode . . . . . . . . . . . . . . . 30 2.6 reset output (nreset) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 2.7 operational amplifiers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 2.8 lin bus interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 2.8.1 error handling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 2.8.2 wake up (from lin) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 2.8.3 lin pull-up . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 2.9 high speed can bus transceiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 L99PM72PXP contents doc id 023553 rev 3 3/128 2.9.1 can transceiver operating modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 2.9.2 sequence for enabling selective wakeup . . . . . . . . . . . . . . . . . . . . . . . . 37 2.9.3 can error handling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 2.9.4 wake up by can . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 2.9.5 can receive only mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 2.9.6 can looping mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 2.10 serial peripheral interface (st spi standard 3.0) . . . . . . . . . . . . . . . . . . 40 3 protection and diagnosis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 3.1 power supply fail . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 3.1.1 v s overvoltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 3.1.2 v s undervoltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 3.2 temperature warning and thermal shut-down . . . . . . . . . . . . . . . . . . . . . 44 3.3 high side driver outputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 3.4 low side driver outputs rel1, rel2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 3.5 spi diagnosis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 4 typical application . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 5 electrical specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 5.1 absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 5.2 esd protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 5.3 thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 5.4 package and pcb thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 5.4.1 powersso-36 thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 5.5 electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 5.5.1 supply and supply monitoring . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 5.5.2 oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 5.5.3 power-on reset (v s ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 5.5.4 voltage regulator v 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 5.5.5 voltage regulator v 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 5.5.6 reset output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 5.5.7 watchdog . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 5.5.8 high side outputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 5.5.9 relay drivers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 5.5.10 wake up inputs (wu1 ... wu3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 contents L99PM72PXP 4/128 doc id 023553 rev 3 5.5.11 high speed can transceiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 5.5.12 lin transceiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 5.5.13 operational amplifier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 5.5.14 spi . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 5.5.15 inputs txdc and txdl for flash mode . . . . . . . . . . . . . . . . . . . . . . . . . 72 6 st spi . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 6.1 spi communication flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 6.1.1 general description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 6.1.2 operating code definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 6.1.3 global status register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 6.1.4 configuration register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 6.1.5 address mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 6.1.6 write operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 6.1.7 format of data shifted out at sdo during write cycle . . . . . . . . . . . . . . 80 6.1.8 read operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81 6.1.9 format of data shifted out at sdo during read cycle . . . . . . . . . . . . . . 82 6.1.10 read and clear status operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83 6.1.11 read device information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84 6.2 spi registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86 6.2.1 overview command byte . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86 6.2.2 overview control register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87 6.2.3 control register 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91 6.2.4 control register 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95 6.2.5 control register 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96 6.2.6 control register 4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98 6.2.7 control register 5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 6.2.8 control register 6 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102 6.2.9 control register 7 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104 6.2.10 control register 8 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105 6.2.11 control register 9 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106 6.2.12 control register 10 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107 6.2.13 control register 11 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107 6.2.14 control register 12 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108 6.2.15 control register 13 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108 6.2.16 control register 14 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109 6.2.17 control register 15 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110 L99PM72PXP contents doc id 023553 rev 3 5/128 6.2.18 control register 16 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111 6.2.19 control register 34 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113 6.2.20 control register 35 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114 6.2.21 overview status register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115 6.2.22 global status register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116 6.2.23 status register 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117 6.2.24 status register 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119 6.2.25 status register 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120 6.2.26 status register 4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122 6.2.27 status register 5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124 7 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125 7.1 ecopack ? . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125 7.2 powersso-36 mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125 8 revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127 list of tables L99PM72PXP 6/128 doc id 023553 rev 3 list of tables table 1. device summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 table 2. pin definitions and functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 table 3. can wake-up signalization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 table 4. wake up from standby modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 0 table 5. functional overview (truth table). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 table 6. fail-safe conditions and exit modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 table 7. persisting fail safe conditions and exit modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 table 8. pwm configuration for high-side outputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 table 9. absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 table 10. esd protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 table 11. operating junction temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 table 12. temperature warning and thermal shutdown . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 table 13. thermal parameter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 table 14. supply and supply monitoring. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 table 15. oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 table 16. power-on reset (v s ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 table 17. voltage regulator v 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 table 18. voltage regulator v 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 table 19. reset output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 table 20. watchdog . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 table 21. output (out_hs) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 table 22. outputs (out1...4) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 table 23. relay drivers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 table 24. wake-up inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 table 25. can communication operating range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 table 26. can transmit data input: pin txdc. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 table 27. can receive data output: pin rxdc . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 3 table 28. can transmitter and receiver: pins canh and canl . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 table 29. can transceiver timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 table 30. lin transmit data input: pin txd . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 table 31. lin receive data output: pin rxd . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 table 32. lin transmitter and receiver: pin lin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 table 33. lin transceiver timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 table 34. lin pull-up: pin linpu . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 table 35. operational amplifier. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 table 36. input: csn . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 table 37. inputs: clk, di . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 table 38. di timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 table 39. output: do . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 table 40. do timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 table 41. csn timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 table 42. rxdl/nint, rxdc/nint timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 2 table 43. inputs: txdc and txdl for flash mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 table 44. command byte . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 table 45. operating code definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 table 46. global status register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 table 47. configuration register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 table 48. address mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 L99PM72PXP list of tables doc id 023553 rev 3 7/128 table 49. write command format: command byte . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 table 50. write command format: data byte 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80 table 51. write command format: data byte 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80 table 52. format of data shifted out at sdo during write cycle: global status register . . . . . . . . . . . 80 table 53. format of data shifted out at sdo during write cycle: data byte 1 . . . . . . . . . . . . . . . . . . . 80 table 54. format of data shifted out at sdo during write cycle: data byte 2 . . . . . . . . . . . . . . . . . . . 80 table 55. read command format: command byte . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81 table 56. read command format: data byte 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81 table 57. read command format: data byte 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81 table 58. format of data shifted out at sdo during read cycle: global status register. . . . . . . . . . . . 82 table 59. format of data shifted out at sdo during read cycle: data byte 1 . . . . . . . . . . . . . . . . . . . 82 table 60. format of data shifted out at sdo during read cycle: data byte 2 . . . . . . . . . . . . . . . . . . . 82 table 61. read and clear status command format: command byte . . . . . . . . . . . . . . . . . . . . . . . . . . 83 table 62. read and clear status command format: data byte 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83 table 63. read and clear status command format: data byte 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83 table 64. format of data shifted out at sdo during read and clear status: global status register . . . 83 table 65. format of data shifted out at sdo during read and clear status: data byte 1. . . . . . . . . . . 83 table 66. format of data shifted out at sdo during read and clear status: data byte 2. . . . . . . . . . . 84 table 67. read device information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84 table 68. id-header . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85 table 69. family identifier. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85 table 70. silicon version identifier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85 table 71. spi-frame-id . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86 table 72. spi register: command byte . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86 table 73. spi register: mode selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86 table 74. spi register: ctrl register selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86 table 75. spi register: stat register selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87 table 76. overview of control register data bytes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87 table 77. control register 1: command and data bytes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91 table 78. control register 1, data bytes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91 table 79. control register 1, bits. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92 table 80. control register 2: command and data bytes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95 table 81. control register 2, data bytes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95 table 82. control register 2, bits. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95 table 83. control register 3: command and data bytes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96 table 84. control register 3, data bytes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96 table 85. control register 3, bits. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96 table 86. control register 4: command and data bytes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98 table 87. control register 4, data bytes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98 table 88. control register 4, bits. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98 table 89. control register 5: command and data bytes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 table 90. control register 5, data bytes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 table 91. control register 5, bits. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101 table 92. control register 6: command and data bytes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102 table 93. control register 6, data bytes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102 table 94. control register 6, bits. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102 table 95. control register 7: command and data bytes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104 table 96. control register 7, data bytes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104 table 97. control register 7, bits. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104 table 98. control register 8: command and data bytes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105 table 99. control register 8, data bytes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105 table 100. control register 8, bits. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105 list of tables L99PM72PXP 8/128 doc id 023553 rev 3 table 101. control register 9: command and data bytes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106 table 102. control register 9, data bytes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106 table 103. control register 9, bits. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106 table 104. control register 10: command and data bytes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107 table 105. control register 10, data bytes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107 table 106. control register 10, bits. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107 table 107. control register 11: command and data bytes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107 table 108. control register 11, data bytes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107 table 109. control register 11, bits. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107 table 110. control register 12: command and data bytes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108 table 111. control register 12, data bytes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108 table 112. control register 12, bits. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108 table 113. control register 13: command and data bytes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108 table 114. control register 13, data bytes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108 table 115. control register 13, bits. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108 table 116. control register 14: command and data bytes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109 table 117. control register 14, data bytes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109 table 118. control register 14, bits. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109 table 119. control register 15: command and data bytes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110 table 120. control register 15, data bytes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110 table 121. control register 15, bits. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110 table 122. control register 16: command and data bytes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111 table 123. control register 16, data bytes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111 table 124. control register 16, bits. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111 table 125. control register 34: command and data bytes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113 table 126. control register 34, data bytes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113 table 127. control register 34, bits. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113 table 128. control register 35: command and data bytes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114 table 129. control register 35, data bytes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114 table 130. control register 35, bits. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114 table 131. overview of status register data bytes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115 table 132. global status register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116 table 133. status register 1: command and data bytes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117 table 134. control register 1, data bytes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117 table 135. status register 1, bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117 table 136. status register 2: command and data bytes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119 table 137. control register 2, data bytes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119 table 138. status register 2, bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119 table 139. status register 3: command and data bytes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120 table 140. control register 3, data bytes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120 table 141. status register 3, bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120 table 142. status register 4: command and data bytes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122 table 143. control register 4, data bytes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122 table 144. status register 4, bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122 table 145. status register 5: command and data bytes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124 table 146. control register 5, data bytes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124 table 147. status register 5, bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124 table 148. powersso-36 mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 26 table 149. document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127 L99PM72PXP list of figures doc id 023553 rev 3 9/128 list of figures figure 1. block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 figure 2. pin connection (top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 figure 3. voltage source with external pnp . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 figure 4. voltage source with external pnp and current limitation . . . . . . . . . . . . . . . . . . . . . . . . . . 14 figure 5. voltage source with external npn . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 figure 6. voltage source with external npn and current limitation . . . . . . . . . . . . . . . . . . . . . . . . . . 15 figure 7. voltage regulator behaviour and diagnosis during supply voltage ramp-up / ramp-down conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 figure 8. sequence to enter and exit sw debug mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 figure 9. main operating modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 figure 10. watchdog in normal operating mode (no errors) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 figure 11. watchdog with error conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 figure 12. watchdog in flash mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 figure 13. change watchdog timing within long open window . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 figure 14. change watchdog timing within window mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 figure 15. general procedure to change watchdog timing out of fail safe mode . . . . . . . . . . . . . . . . 28 figure 16. change watchdog timing out of fail safe mode (watchdog failure) . . . . . . . . . . . . . . . . . . 28 figure 17. example: exit fail-safe mode from watchdog failure. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 figure 18. master node configuration using lin_pu (optional) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 figure 19. transceiver state diagram if selective wake-up is disabled (cr16 sw_en = 0) . . . . . . . . 35 figure 20. can transceiver state diagram if selective wake-up is enabled (cr16 sw_en = 1). . . . . 36 figure 21. can wake up capabilities . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 figure 22. overvoltage and undervoltage protection and diagnosis . . . . . . . . . . . . . . . . . . . . . . . . . . 43 figure 23. thermal shutdown protection and diagnosis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 figure 24. phase shifted pwm . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 figure 25. typical application diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 figure 26. thermal data of powersso-36. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 figure 27. powersso-36 pc board. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 figure 28. powersso-36 thermal resistance junction to ambient vs pcb copper area (v 1 on) . . . . 53 figure 29. powersso-36 thermal impedance junction to ambient vs pcb copper area (single pulse with v 1 on) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 3 figure 30. powersso-36 thermal fitting model (v 1 on) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 figure 31. watchdog timing (long, early, late and safe window) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 figure 32. watchdog early, late and safe windows . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 figure 33. lin transmit, receive timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 figure 34. spi - transfer timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 figure 35. spi input timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 figure 36. spi output timing (part 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 figure 37. spi csn - output timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 figure 38. spi - csn low to high transition and global status bit access . . . . . . . . . . . . . . . . . . . . . . 75 figure 39. read configuration register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78 figure 40. write configuration register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78 figure 41. format of data shifted out at sdo during write cycle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81 figure 42. format of data shifted out at sdo during read cycle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82 figure 43. format of data shifted out at sdo during read and clear status operation . . . . . . . . . . . . 84 figure 44. powersso-36 package dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125 block diagram and pin description L99PM72PXP 10/128 doc id 023553 rev 3 1 block diagram and pin description figure 1. block diagram ' , : l q g r z : d w f k g r j 9 v $ * 1 ' 9 : 8 & 6 1 & / . ' 2 2 8 7 b + 6 2 8 7 5 ( / 5 ( / : 8 7 h p s 3 u h z d u q l q j 6 k x w g r z q 8 q g h u y r o w d j h 2 y h u y r o w d j h 6 k x w g r z q 5 [ ' b / 1 , 1 7 7 [ ' b / 1 5 h v h w 9 5 ( * 9 p $ 9 2 8 7 / , 1 / , 1 3 8 2 3 2 3 2 3 b r x w 2 3 2 3 2 3 b r x w + 6 & $ 1 , 6 2 7 [ ' b & 5 [ ' b & 1 , 1 7 & $ 1 b + & $ 1 b / 2 8 7 ) 6 2 3 * 1 ' : 8 & $ 1 6 x s s o \ 9 5 ( * 9 p $ 6 3 , 2 8 7 / r z 6 l g h p $ 2 x w s x w & o d p s + l j k 6 l g h p $ / , 1 f h u w l i l h g / , 1 6 $ ( - / r z 6 l g h p $ 2 x w s x w & o d p s + l j k 6 l g h p $ + l j k 6 l g h p $ + l j k 6 l g h p $ + l j k 6 l g h p $ 7 l p h u 7 l p h u : d n h 8 s , q : d n h 8 s , q : d n h 8 s , q f k d q q h o 3 : 0 * h q h u d w r u % l w w l p h / r j l f ' d w d , ' ) l o w h u / 2 * , & 2 v f 1 & ( " 1 ( $ ' 5 L99PM72PXP block diagram and pin description doc id 023553 rev 3 11/128 table 2. pin definitions and functions pin symbol function 1 agnd analog ground 2 rxdc/nint rxdc -> can receive data output nint -> indicates remote can wake-up events in active mode (transceiver in trx_stby; can_act = 0) 3 txdc can transmit data input 4 canh can high level voltage i / o 5 canl can low level voltage i / o 6n.c.tbc 7 cansup can supply input; to allow external can supply from v 1 or v 2 regulator. 8 nreset n reset output to microcontroller; internal pull-up of typ. 100 k ? (reset state = low) 9 v1 voltage regulator 1 output: 5 v supply e.g. micro controller, can transceiver 10 v2 voltage regulator 2 output: 5 v suppl y for external loads (ir receiver, potentiometer, sensors) or can transceiver. v 2 is protected against reverse supply. 11 txdl lin transmit data input 12 rxdl/nint rxdl -> lin receive data output nint -> indicates local/remote wake-up events except can wake-up in active mode provides a programmable timer interrupt signal 13 op2+ non inverting input of operational amplifier 2 14 op2- inverting input of operational amplifier 2 15 op2_out output of operational amplifier 2 16 di spi: serial data input 17 do spi: serial data output 18 clk spi: serial clock input 19 csn spi: chip select not input 20?22 wu1?3 wake-up inputs 1?3: input pins for stat ic or cyclic monitoring of external contacts 23 op1_out output of operational amplifier 1 24 op1- inverting input of operational amplifier 1 25 op1+ non inverting input of operational amplifier 1 26 out4 high side driver output (7 ? , typ) 27 out3/fso configurable as: ? high-side driver output (7 ? , typ) ? fail safe output pin (default) 28 out2 high side driver output (7 ? , typ) 29 out1 high side driver output (7 ? , typ) 30 out_hs high side driver (1 ? , typ) block diagram and pin description L99PM72PXP 12/128 doc id 023553 rev 3 figure 2. pin connection (top view) 31 v s power supply voltage 32 linpu high side driver output to s witch off lin master pull up resistor 33 lin lin bus line 34 rel1 low side driver output (2 ? typ) 35 rel2 low side driver output (2 ? typ) 36 pgnd power ground (rel1/2, lin and can gnd), to be connected to agnd externally table 2. pin definitions and functions (continued) pin symbol function canh do clk v2 out_hs agnd 1 rxdc / nint 2 txdc 3 4 5 nreset 6 v1 7 8 txdl 9 rxdl / nint 10 op2p 11 op2m 12 opou t 2 13 di 14 n.c . 15 cansup 16 17 18 pgnd 36 vs 35 rel1 34 rel2 33 32 out3/fso 31 out1 30 29 out4 28 op1p 27 op1m 26 opout1 25 wu3 24 wu2 23 wu1 22 csn 21 linpu 20 lin 19 out2 powersso-36 canl tab = agnd L99PM72PXP detailed description doc id 023553 rev 3 13/128 2 detailed description 2.1 voltage regulators the L99PM72PXP contains tw o independent and fully protected low drop voltage regulators, which are designed for very fast transient response and do not require electrolytic output capacitors for stability. the output voltage is stable with ceramic load capacitors ? 220 nf. 2.1.1 voltage regulator: v 1 the v 1 voltage regulator provides 5 v supply voltage and up to 250 ma continuous load current and is mainly intended for supply of the system microcontroller. the v 1 regulator is embedded in the power management and fail_safe functionality of the device and operates according to the selected operating mode. it can be used to supply the internal hs can transceiver via the cansup pin externally. in case of a short circuit condition on the can bus, the output current of the transmitter is limited to 100 ma and the transceiver is turned off in order to ensure continued supply of the microcontroller. in addition the regulator v 1 drives the L99PM72PXP internal 5 v loads. the voltage regulator is protected against overload and overtemperature. an external reverse current protection has to be provided by the application circuitry to prevent the input capacitor from being discharged by negative transients or low input voltage. current limitation of the regulator ensures fast charge of external bypass capacitors. the output voltage is stable for ceramic load capacitors ? 220 nf. if the device temperature exceeds the tsd1 threshold, all outputs (outx, relx, v2, lin) are deactivated except v 1 . hence the micro controller has th e possibility for interaction or error logging. in case of exceeding tsd2 threshold (tsd2 > tsd1), also v 1 is deactivated (see figure 23: thermal shutdown protection and diagnosis ). a timer is started and the voltage regulator is deactivated for t tsd = 1 sec. during this time, all other wakeup sources (can, lin, wu1...3 and wake up of c by timer) are disabled. after 1 sec, the voltage regulator tries to restart automatically. if the restart fails 7 times, within one minute, without clearing and thermal shutdown condition st ill exists, the L99PM72PXP enters the forced v bat_standby mode. in case of short to gnd at "v 1 " after initial turn on (v 1 <2v for t>t v1 short ) the L99PM72PXP enters the forced v bat_standby mode. reactivation (wake-up) of the device can be achieved with signals from can, lin, wu1..3 or periodic wake by timer. 2.1.2 voltage regulator: v 2 the voltage regulator v 2 can supply additional 5 v loads (e.g. logic components or the integrated hs can transceiver or external loads such as sensors or potentiometers. the maximum continuous load current is 100 ma. the regulator is protected against: overload overtemperature short circuit (short to ground and battery supply voltage) reverse biasing detailed description L99PM72PXP 14/128 doc id 023553 rev 3 2.1.3 increased output current cap ability for voltage regulator v 2 for applications, which require high output currents, the output current capability of the regulator can be increased my means of the integrated operational amplifiers and an external pass transistor. figure 3. voltage source with external pnp figure 4. voltage source with external pnp and current limitation figure 3 shows a possible configuration with a pnp pass element using voltage regulator 2 to provide the voltage reference for the regulated output voltage v3. the v s operating range for this circuit is 5.5 v to 18 v. it is important respect the input common mode range specified for the operational amplifiers. the output voltage v3 can be calculated using the following formula (for r3 = r4): 9 & l & & h p & 9 v 9 & / 3 0 5 5 5 e 5 5 5 0 - ' & 2 3 [ b 2 8 7 2 3 [ 2 3 [ ( " 1 ( $ ' 5 9 & l & & h p & 9 v 9 & / 3 0 5 5 5 e 5 5 5 0 - ' & 5 % & 2 3 [ b 2 8 7 2 3 [ 2 3 [ ( " 1 ( $ ' 5 v 3 v 2 2 ------ - r 1 r 2 + r 2 -------------------- - v ?? ? = L99PM72PXP detailed description doc id 023553 rev 3 15/128 the circuit in figure 4 provides additional current limitation using an additional pnp transistor and r6, which allo ws setting the current limit. figure 5. voltage source with external npn figure 6. voltage source with external npn and current limitation figure 5 shows a possible configuration with an npn pass element using voltage regulator 2 to provide the voltage reference for the regulated output voltage v3. this circuit requires fewer components compared to the configuration in figure 3 but has a limited v s operating range (6 v to 18 v). the output voltage v3 can be calculated using the following formula (for r3 = r4): the circuit in figure 6 provides additional current limitation using an additional npn transistor and r5 which allo ws setting the current limit. 9 & l & & h p & 9 v 9 & / 3 0 5 5 5 0 - ' & 2 3 [ b 2 8 7 2 3 [ 2 3 [ 5 ( " 1 ( $ ' 5 9 & l & & h p & 9 v 9 & / 3 0 5 5 5 5 5 0 - ' & % & 2 3 [ b 2 8 7 2 3 [ 2 3 [ ( " 1 ( $ ' 5 v 3 v 2 2 ------ - r 1 r 2 + r 2 -------------------- - v ?? ? = detailed description L99PM72PXP 16/128 doc id 023553 rev 3 alternatively, voltage regulator 1 can be used to provide the 5 v reference for this topology. however, the additional current consumption through r3 and r4 has to be considered in v 1_standby mode. 2.1.4 voltage regulator failure the v 1 and v 2 regulator output voltages are monitored. in case of a drop below the v 1 , v 2 - fail thresholds (v 1,2 < 2 v, typ for t > 2 s), the v 1,2 -fail bits are latched. the fail bits can be cleared by a dedicated spi command. short to ground detection if 4 ms after turn on of the regulator the v 1,2 voltage is below the v 1,2 fail thresholds, (independent for v 1,2 ), the L99PM72PXP identifies a short circuit condition at the related regulator output and the regulator are switched off. in case of v 1 short to gnd failure the device enters v bat_standby mode automatically. bits forced vbat tsd2/shtv1 and v 1_fail were set. in case of a v 2 short to gnd failure the v 2 short and v 2 fail bit is set. if the output voltage of the corresponding regulator once exceeded the v 1,2_fail thresholds the short to ground detection is disabled. if a short to ground condition occurs the regulator outputs switch of due to thermal shutdown (v 1 at tsd2; v 2 at tsd1). L99PM72PXP detailed description doc id 023553 rev 3 17/128 2.1.5 voltage regulator behavior figure 7. voltage regulator behaviour and diagnosis during supply voltage ramp-up / ramp- down conditions 2.2 operating modes the L99PM72PXP can be operated in 4 different operating modes: active flash v 1_standby v bat_standby a cyclic monitoring of wake-up inputs and a peri odic interrupt / wake-up by timer is available in stand-by modes. 2.2.1 active mode all functions are available and the device is controlled by the st spi interface. 2.2.2 flash mode to program the system microcon troller via lin or hs can bus signals, the device can be operated in lin flash mode or can flash mode where the internal watchdog is disabled. 9 v > 9 @ 9 > 9 @ 1 u h v h w > 9 @ 9 1 9 ' 3 9 3 2 5 & r o g 6 w d u w e l w l v v h w x v 9 5 7 + + l j k / r z 3 r z h u r q 5 h v h w w k u h v k r o g 9 i d l o , i w ! w y v k r u w 9 v k r u w g h w h f w h g ? 9 e d w w v w d q g e \ 9 i d l o e l w l v v h w 9 v x y e l w l v w v h w w w x y w 5 5 w 5 5 w ! w x y 1 r 5 h v h w j h q h u d w h g w ! w x y 6 s h f l i l f d w l r q 3 d u d p h w h u v w u g w u g 9 6 8 9 , q d f w l y h $ f w l y h , q d f w l y h 5 h d g & o h d u ) 6 2 % l w 9 1 & r q w u r o 5 h j l v w h u v d u h v h w w r g h i d x o w y d o x h v ' l v d e o h g ' l v d e o h g 9 $ % 6 p l q + l j k = * u r x q g h g & r q w u r o 5 h j l v w h u v d u h v h w w r g h i d x o w y d o x h v ) d l o 6 d i h 2 x w s x w w ! w y i d l o w x y 9 x q g h u y r o w d j h i l o w h u w l p h w y i d l o 9 i d l o i l o w h u w l p h w y v k r u w 9 v k r u w i l o w h u w l p h w 5 5 5 h v h w s x o v h u h d f w l r q w l p h w u g 5 h v h w s x o v h g x u d w l r q 9 v 8 9 9 v x q g h u y r o w d j h w k u h v k r o g 9 s r u 9 v s r z h u r q u h v h w w k u h v k r o g 9 u w k 9 u h v h w w k u h v k r o g 9 i d l o 9 i d l o w k u h v k r o g $ * 9 detailed description L99PM72PXP 18/128 doc id 023553 rev 3 moreover, in flash mode the do-output is a test output and cannot be used for device communication. all other device features in flash mode are available as in active mode. the can-receiver is enabled in can flash mode by default; the can transmitter has to be enabled by setting the can_act bit to ?1?. a transition from flash modes to v 1_standby or v bat_standby is not possible. the modes can be entered by applying an external voltage at the respective pin: v txdl > v flash (can flash mode) v txdc > v flash (lin flash mode) at exit from flash modes (v txd L99PM72PXP detailed description doc id 023553 rev 3 19/128 a cyclic supply of external contacts and a sy nchronized monitoring of the contact state can be activated and configured by spi. in v 1_standby mode various wake-up sources can be individually programmed. each wake- up event puts the device into active mode and forces the rxdl/nint pin to a low level indicating the wake-up condition to the microcontroller. after power on reset (por) all wake up sources are activated by default except the periodic interrupt / wake timer. with the interrupt timer the micro controller can be forced from 'stop' to 'run' after a programmable period. the rxdl/nint pin is forced low after the timer is elapsed. the L99PM72PXP enters active mo de and is awaiting a valid watchdog trigger. both internal timers can be used for this feature. the interrupt timer (tint) at pin rxdl/nint is only available in v 1_standby mode. note: inputs txdl, txdc must be at recessive (high) level and csn must be at high level or at high impedance in order to achieve minimum standby current in v 1_standby mode. inputs di and clk must be at gnd or at high impedance to achieve minimum standby current in v 1_standby mode. 2.2.5 interrupt the interrupt signal (linked to rxdl/nint) indicates a wake-up event from v 1_standby mode. in case of a wake-up by wake-up inputs, activity on lin or can, spi access or timer- interrupt the rxdl/nint pin is pulled low for t = t interrupt . when can_act = 0 (during v 1_standby mode or active mode) a wup (sw_en = 0) or a wuf (sw_en = 1) generates an interrupt on rxdc/nint to signalize can communication on the bus to the c. in case of a can communication timeout an interrupt at rxdc /nint is generated and the can_to flag is set. in case of v 1_standby mode and (i v1 >i cmp ), the device remains in standby mode, the v 1 regulator switches to high current mode and the watchdog starts. no interrupt signal is generated. table 3. can wake-up signalization operating mode event wake-up transition to active status flag interrupt transceiver state active wup or wuf (1) not applicable wake_can wup or wup/wuf rxdc trx_stby can timeout can_to rxdc trx_stby v 1_standby wup or wuf (1) ye s wake_can wup or wup/wuf rxdl trx_stby can timeout no can_to rxdc trx_stby detailed description L99PM72PXP 20/128 doc id 023553 rev 3 2.2.6 v bat_standby mode the transition from active mode to v bat_standby mode is initiated by an spi command. in v bat_standby mode, the v 1 voltage regulator, relay outputs, lin and can transmitters are switched off. high side outputs and the v 2 regulator remain in the configuration programmed prior to the standby command. in v bat_standby mode the current consumption of th e L99PM72PXP is reduced to a minimum level. an n reset pulse is generated upon wake-up from v bat_standby mode. note: inputs txdl, txdc and csn mu st be terminated to gnd in v bat_standby to achieve minimum standby current. this can be achieved with the internal esd protection diodes of the microcontroller (microcontroller is not s upplied in this mode; v 1 is pulled to gnd). 2.2.7 wake up from standby modes a wake-up from standby mode switches the device to active mode. this can be initiated by one or more of the following events: v bat_standby wup or wup/wuf (2) ye s wake_can wup/wuf not applicable trx_stby can timeout transition to trx_sleep can_to trx_sleep 1. sw_en = 0: ? wake-up according iso 11898-5 (wup) ? flags: wake_can, wup sw_en = 1: ? wake-up according iso 11898-6 (wup) ? flags: wake_can, wup, wuf (the wup flag is se t only if the received wuf also contained a wup) 2. sw_en = 0: ? wake-up according iso 11898-5 (on wup) ? flags: wake_can, wup sw_en = 1: ? wake-up according iso 11898- 6 (on wup/wuf combination) ? after the reception of a wake-up pattern (wup) t he can enhanced voltage biasing is turned on until a can timeout is detected ? flags: wake_can, wup, wuf table 3. can wake-up signalization (continued) operating mode event wake-up transition to active status flag interrupt transceiver state table 4. wake up from standby modes wake up source description lin bus activity can be disabled by spi can bus activity can be disabled by spi selective wake-up can be configured by spi level change of wu1 - 3 can be individually configured or disabled by spi L99PM72PXP detailed description doc id 023553 rev 3 21/128 to prevent the system from a deadlock condition (no wake up possible) a configuration where the periodic timer interrupt and wake up by lin and hs can are disabled, is not allowed. the default configuration is entered for all wake-up sources in case of such an invalid setting. all wake-up events from v 1_standby mode (except i v1 > i cmp ) are indicated to the microcontroller by a low-pulse (duration: 56 s) at rxdl/nint or rxdc/nint (see ta b l e 3 : can wake-up signalization ) wake-up from v 1_standby by spi access might be used to check the interrupt service handler. 2.2.8 wake up inputs the de-bounced digi tal inputs wu1...wu3 can be used to wake up the L99PM72PXP from standby modes. these inputs are sensitive to any level transition (positive and negative edge) for static contact monitoring, a filter time of 64s is implemented at wu1-3. the filter is started when the input voltage passes the specified threshold. in addition to the continuous sensing (static contact monitoring) at the wake up inputs, a cyclic sense functionality is implemented. this feature allows periodical activation of the wake-up inputs to read the status of the external contacts. the periodical activation can be linked to timer 1 or timer 2 (see section 2.2.9 ). the input signal is filtered with a filter time of 16 s after a programmable delay (80 s or 800 s) according to the configured timer on-time. a wake-up is processed if the status has changed versus the previous cycle. the outputs out_hs and out1-4 can be used to supply the external contacts with the timer setting according to the cyclic monitoring of the wake-up inputs. if the wake-up inputs are configured for cyclic sense mode the input filter timing and input filter delay ( wux_filt in control register 2) must correspond to the setting of the high side output which supplies the external contact switches (outx in control register 0). in standby mode, the inputs wu1-3 are spi configurable for pull-up or pull-down current source configuration according to the setup of the external. in active mode the inputs have a pull down resistor. in active mode, the input status can be read by spi (status register 2). static sense should be configured (control register 2) before the read operation is started (in cyclic sense i v1 >i cmp device remains in v 1_standby mode but watchdog is enabled (if i cmp =0) and the v 1 regulator goes into high curr ent mode (increased current consumption). no interrupt is generated. timer interrupt / wake up of c by timer programmable by spi ?v 1_standby mode: device wakes up and interrupt signal is generated at rxdl/nint when programmable timeout has elapsed ?v bat_standby mode: device wakes up, v 1 regulator is turned on and n reset signal is generated when programmable timeout has elapsed spi access always active (except in v bat_standby mode) wake up event: csn is low and first rising edge on clk table 4. wake up from standby modes (continued) wake up source description detailed description L99PM72PXP 22/128 doc id 023553 rev 3 configuration, the input status is updated acco rding to the cyclic sense timing; therefore, reading the input status in this mode may not reflect the actual status). 2.2.9 cyclic contact supply in v 1_standby and v bat_standby modes, any high side driver output (out1..4, ouths) can be used to periodically supply external contacts. the timing is selectable by spi timer 1: period is x s. the on-time is 10 ms resp. 20 ms: with x ? {1, 2, 3, 4s} timer 2: period is x ms. the on-time is 100 s resp. 1 ms: with x ? {10, 20, 50, 200 ms} timer 1 and timer 2 are re-started with every valid write command to cr3 (csn low to high transition). the timers start with the off-phase. 2.2.10 timer interrupt / wake- up of microcontroller by timer during standby modes the cyclic wake up feature, configured via spi, allows waking up the c after a programmable timeout according to timer1 or timer 2. from v 1_standby mode, the L99PM72PXP wakes up (after the selected timer has elapsed) and sends an interrupt signal (via rxdl/nint pi n) to the c. the device enters active mode and the watchdog is started with a long open window. the microcontroller can send the device back into v 1_standby after finishing its tasks. from v bat_standby mode, the L99PM72PXP wakes up (after the selected timer has elapsed), turns on the v 1 regulator and provides an n reset signal to the c. the device enters active mode and the watchdog is started with a long open window. the microcontroller can send the device back into v bat_standby after finishing its tasks. 2.3 functional overview (truth table) table 5. functional overview (truth table) function comments operating modes active mode v 1_standby static mode (cyclic sense) v bat_standby static mode (cyclic sense) voltage regulator, v 1 vout=5v on on (1) off voltage regulator, v 2 vout=5v on/ off (2) on (2) / off on (2) / off reset generator on on off window watchdog v 1 monitor on off (on: i v1 >i cmp - threshold and i cmp =0) off wake up off active (3) active (3) hs-cyclic supply oscillator time base on / off on (2) / off on (2) / off relay driver on off off L99PM72PXP detailed description doc id 023553 rev 3 23/128 operational amplifiers on off off lin lin 2.1 on off (4) off (4) hs_can on / off (5) off (4) off (4) fso (if configured by spi), active by default fail safe output out3/fso off (6) out3/fso off (6) out3/fso off (6) oscillator on off (7) off (7) v s -monitor on (8) (8) 1. supply the processor in low current mode. 2. only active when selected via spi. 3. unless disabled by spi 4. the bus state is internally stored when going to st andby mode. a change of bus state leads to a wake-up after exceeding of internal filter ti me (if wake-up by lin or can is not disabled by spi). selective wake functionality if enabled by spi 5. after power-on, the hs can tran sceiver is in ?can trx standby? m ode. it is activated by spi command (can_act = 1) 6. on in failsafe condition: if standby mode is entered with active fail safe mode, the output remains on in standby mode. 7. on, if cyclic sense is enabled. 8. cyclic activation = puls ed on during cyclic sense table 5. functional overview (truth table) (continued) function comments operating modes active mode v 1_standby static mode (cyclic sense) v bat_standby static mode (cyclic sense) detailed description L99PM72PXP 24/128 doc id 023553 rev 3 figure 9. main operating modes 2.4 configurable window watchdog during normal operation, the watchdog monitors the micro controller within a programmable trigger cycle: (10 ms, 50 ms, 100 ms, 200 ms) in v bat_standby and flash program modes, the watchdog circuit is automatically disabled. in v 1_standby mode a wake up by timer is programmable in order to wake up the c (see section 2.2.10 ). after wake-up, the watchdog starts with a long open window. after serving the watchdog, the microcontroller may send the device back to v 1_standby mode. after power-on or standby mode, the watchdog is started with a long open window (65 ms nominal). the long open window allows the micro controller to run its own setup and then to trigger the watchdog via the spi. the trigge r is processed when the csn input becomes high after the transmission of the spi word. writing '1' to the watchdog trigger bit terminates the long open window and start the window watchdog (the timing is programmable by spi). subsequently, the micro controller has to $ f w l y h 0 r g h 9 2 1 5 h v h w * h q h u d w r u d f w l y h : d w f k g r j d f w l y h 9 6 w d q g e \ 0 r g h 9 2 1 5 h v h w * h q h u d w r u d f w l y h : d w f k g r j 2 ) ) l i , y , f p s r u , & 0 3 9 e d w 6 w d q g e \ 0 r g h 9 2 ) ) 5 h v h w * h q h u d w r u 2 ) ) 1 u h v h w o r z : d w f k g r j 2 ) ) : d n h x s ( y h q w : d n h x s ( y h q w 6 3 , f r p p d q g 9 e d w v w d u w x s $ o o u h j l v w h u v 6 h w w r g h i d x o w & k l s 5 h v h w e l w * 6 5 e l w d f w l y h 9 v ! 9 s r u [ 7 k h u p d o 6 k x w g r z q 7 6 ' 2 5 [ : ' i d l o ) o d v k 0 r g h : d w f k g r j 2 ) ) 9 7 ; ' / ! 9 i o d v k 2 5 9 7 ; ' & ! 9 i o d v k 9 7 ; ' / ! 9 i o d v k 2 5 9 7 ; ' & ! 9 i o d v k 9 7 ; ' / 9 i o d v k $ 1 ' 9 7 ; ' & 9 i o d v k 9 7 ; ' / ! 9 i o d v k 2 5 9 7 ; ' & ! 9 i o d v k 6 3 , f r p p d q g 2 5 [ 7 k h u p d o 6 k x w g r z q 2 5 9 v k r u w w r * 1 ' 9 9 i r u p v d i w h u v z l w f k 2 1 2 5 [ : ' ) d l o x u h $ * 9 L99PM72PXP detailed description doc id 023553 rev 3 25/128 serve the watchdog by alternating the watchdog trigger bit within the safe trigger area (refer to figure 32 ). a correct watchdog trigger signal immediately starts the next cycle. after 8 watchdog failures in sequence, the v 1 regulator is switched off for 200 ms. if subsequently, 7 additional watchdog failures occur, the v 1 regulator is comp letely turned off and the device goes into v bat_standby mode until a wakeup occurs. in case of a watchdog failure, the outputs (relx, outx, v2) are switched off and the device enters fail_safe mode (i. e. all control registers are set to default values except the 'out3 control bit'). the following diagrams illustrate the watchdog behavior of th e L99PM72PXP. the diagrams are split into 3 parts. first diagram shows the functional behavior of the watchdog without any error. the second diagram covers the behavior covering all the error conditions, which can affect the watchdog behavior. third diagram shows the transition in and out of flash mode. all 3 diagrams can be overlapped to get all the possible state transitions under all circumstances. for a be tter readability, they were split in normal operating, operating with errors and flash mode. figure 10. watchdog in normal operating mode (no errors) 7 $ / & & l o n g o p e n w i n d o w 7 i n d o w - o d e p r o p p e r t r i g g e r i n 7 i n d o w m o d e 4 2 ) ' t g g o 3 t a n d b y 7 a k e u p ! . $ 6 6 r s t t h r 6 6 r s t t h r 6 " ! 4 3 t a n d b y 6 3 t a n d b y ! c t i v e m o d e ! c t i v e m o d e 6 3 t b y ! . $ ) 6 ) # - 0 g o 3 t a n d b y 6 3 t b y ! . $ ) 6 ) # - 0 ( " 1 ( $ ' 5 detailed description L99PM72PXP 26/128 doc id 023553 rev 3 figure 11. watchdog with error conditions figure 12. watchdog in flash mode 2.4.1 change watchdog timing there are 4 programmable watchdog timings available, which represent the nominal trigger time in window mode. to change the watchdog timing, a new timing has to be written by spi. the new timing gets active with the next valid watchdog trigger. the following figures illustrate the sequence, which is recommended to use, changing the timing within long open window and within window mode. : ' 2 ) ) o r q j r s h q z l q g r z : l q g r z 0 r g h s u r s s h u w u l j j h u l q : l q g r z p r g h 7 5 , * ? : ' i d l o 7 6 ' : ' i d l o 7 6 ' i r u f h g 9 % $ 7 9 9 u w k 9 9 u w k 9 ! 9 u w k 9 % $ 7 6 w d q g e \ 9 6 w d q g e \ , 9 , & 0 3 i r u f h g 9 % $ 7 [ : ' i d l o [ 7 6 ' 6 k r u w 9 $ f w l y h p r g h $ f w l y h p r g h $ * 9 : ' 2 ) ) o r q j r s h q z l q g r z : l q g r z 0 r g h ) / $ 6 + p r g h ) / $ 6 + p r g h ( [ l w ) / $ 6 + p r g h ) / $ 6 + p r g h $ f w l y h p r g h $ f w l y h p r g h $ * 9 L99PM72PXP detailed description doc id 023553 rev 3 27/128 figure 13. change watchdog timing within long open window figure 14. change watchdog timing within window mode if the device is in fail_safe mode, the control registers are locked for writing. to change the watchdog timing out of fail_safe mode, first the fail_safe condition must be solved, respective confirmed from the microcontroller. afterwards the new watchdog timing can be programmed using the sequence from figure 15 . since the actions to remove, a fail_safe condition can differ from the root cause of the fail safe the following diagram shows the general procedure how to change the watchdog timing out of fail_safe mode. figure 16 shows the procedure to change watchdog timing with a previous watchdog failure, since this is a special fail_safe scenario. o r q j r s h q z l q g r z z l q g r z p r g h > w l p l q j d v s u r j u d p p h g l q s u h y l r x v 6 3 , f r p p d q g h j p v @ & 6 1 z u l w h r s h u d w l r q & w u o 5 h j : ' 7 l p h > h j p v @ ) h h g e d f n ) 6 2 z u l w h r s h u d w l r q d f f h s w h g z u l w h r s h u d w l r q & w u o 5 h j 7 u l j ) h h g e d f n f k h f n ) 6 2 f k d q j h w l p l q j i r u : ' u h d g r s h u d w l r q & w u o 5 h j ) h h g e d f n f k h f n ) 6 2 f k h f n : ' w l p h z u l w h r s h u d w l r q & w u o 5 h j 7 u l j : ' w l p l q j > h j p v @ 6 3 , & r p p d q g 6 3 , ) h h g e d f n : d w f k g r j 0 r g h $ * 9 z l q g r z p r g h > p v @ z u l w h r s h u d w l r q & w u o 5 h j : ' 7 l p h > h j p v @ & 6 1 z u l w h r s h u d w l r q & w u o 5 h j s u r s h u w u l j j h u u h d g r s h u d w l r q & w u o 5 h j z u l w h r s h u d w l r q & w u o 5 h j s u r s h u w u l j j h u : ' w l p h > p v @ z l q g r z p r g h > p v @ z u l w h r s h u d w l r q & w u o 5 h j s u r s s h u w u l j j h u ) h h g e d f n ) 6 2 z u l w h r s h u d w l r q d f f h s w h g ) h h g e d f n f k h f n ) 6 2 f k d q j h w l p l q j i r u : ' ) h h g e d f n f k h f n ) 6 2 f k h f n : ' w l p h : ' w l p h > p v @ 6 3 , & r p p d q g 6 3 , ) h h g e d f n : d w f k g r j 0 r g h $ * 9 detailed description L99PM72PXP 28/128 doc id 023553 rev 3 figure 15. general procedure to change watchdog timing out of fail safe mode figure 16. change watchdog timing out of fail safe mode (watchdog failure) 2.5 fail safe mode 2.5.1 single failures L99PM72PXP enters fail sa fe mode in case of: watchdog failure v 1 turn on failure ?v 1 short (v 1 L99PM72PXP detailed description doc id 023553 rev 3 29/128 the fail safe functionality is also available in v 1_standby mode. during v 1_standby mode the fail safe mode is entered in the following cases: v 1 undervoltage (v 1 detailed description L99PM72PXP 30/128 doc id 023553 rev 3 figure 17. example: exit fail-safe mode from watchdog failure 2.5.2 multiple failures ? entering forced v bat_standby mode if the fail-safe condition persists and all attempts to return to normal system operation fail, the L99PM72PXP enters the forced v bat_standby mode in order to prevent damage to the system. the forced v bat_standby mode can be terminated by any regular wake-up event. the root cause of the forced v bat_standby is indicated in the spi status registers the forced v bat_standby mode is entered in case of: multiple watchdog failures: forced sleep wd = 1 (15 x watchdog failure) multiple thermal shutdown 2: fo rced sleep tsd2/shtv1 = 1 (7 x tsd2) v 1 short at turn-on: forced sleep tsd2/shtv1 = 1 (v 1 L99PM72PXP detailed description doc id 023553 rev 3 31/128 2.6 reset output (nreset) if v 1 is turned on and the voltage exceeds the v 1 reset threshold, the reset output ?nreset? is pulled up by internal pull up resistor to v 1 voltage after a reset delay time (t rd ). this is necessary for a defined start of the mi cro controller when the application is switched on. since the nreset output is realized as an open drain output it is also possible to connect an external nreset open drain nrese t source to the output. as soon as the nreset is released by the l99pm72 the watchdog timing starts with a long open window. a reset pulse is generated in case of: v 1 drops below v rth (configurable by spi) for t > t uv1 watchdog failure turn-on of the v 1 regulator (v s power-on or wake-up from v bat_standby mode) 2.7 operational amplifiers the operational amplifiers are especially designed to be used for sensing and amplifying the voltage drop across ground connected shunt resistors. therefore the input common mode range includes -0.2 v to 3v. the operational amplifiers are designed for -0.2 v to 3 v input voltage swing and rail-to-rail output voltage range. all pins (positive, negative and outputs) are available to be able to operate in non-inverting and inverting mode. both operat ional amplifiers are on-chip compensated for stability over the whole operating range within the defined load impedance. the operational amplifiers may also be used to setup an additional high current voltage source with an external pass element. refer to section 2.1.3 for a detailed description. table 7. persisting fail safe conditions and exit modes failure source failure condition dia gnosis exit from fail_safe mode c (oscillator) 15 consecutive watchdog failures fail_safe = 1; forced_sleep_wd = 1 wake-up trig = 1 during lowi read & clear sr3 v 1 short at turn-on fail_safe = 1; forced_sleep_tsd2_shtv1 = 1 read & clear sr3 after wake-up temperature 7 times tsd2 fail_safe = 1; tw = 1; tsd1 = 1; tsd2 = 1; forced_sleep_tsd2_shtv1=1 read & clear sr3 after wake-up detailed description L99PM72PXP 32/128 doc id 023553 rev 3 2.8 lin bus interface features: speed communication up to 20kbit/s. lin 2.1 compliant (saej2602 compatible) transceiver. gnd disconnection fail safe at module level. off mode: does not disturb network. gnd shift operation at system level. micro controller interface with cmos compatible i/o pins. internal pull-up resistor internal high side switch to disconnect master pull-up resistor in case of short circuit of bus signal (b) esd and transient immunity according to iso7637 and en / iec61000-4-2 matched output slopes and propagation delay in order to further reduce the current consumption in standby mode, the integrated lin bus interface offers an ultra low current consumption. 2.8.1 error handling the L99PM72PXP provides the following thre e error handlin g features which are not described in the lin spec. v2.1, but are realized in different stand alone lin transceivers / micro controllers to switch the application back to normal operation mode. at v s >v por (i.e. v s power-on reset threshold), the lin transceiver is enabled. the lin transmitter is disabled in case of the following errors: dominant txdl time out lin permanent recessive thermal shutdown 1 v s over- / undervoltage the lin receiver is not disabled in case of any failure condition. dominant txdl time out if txdl is in dominant state (low) for more than 12 ms (typ) the transmitter is disabled, the status bit is latched and can be read and optionally cleared by spi. the transmitter remains disabled until the status register is cleared. this feature can be disabled via spi. permanent recessive if txdl changes to dominant (low) state but rxdl signal does not follow within 40 s the transmitter is disabled, the status bit is latched and can be read and optionally cleared by spi. the transmitter remains disabled until the status register is cleared. b. use of the master pull -up switch is optional. L99PM72PXP detailed description doc id 023553 rev 3 33/128 permanent dominant if the bus state is dominant (low) for more than 12 ms a permanent dominant status is detected. the status bit is latched and can be read and optionally cleared by spi. the transmitter is not disabled. 2.8.2 wake up (from lin) in standby mode the l99pm72 pxp can receive a wake up from lin bus. for the wake up feature the L99PM72PXP logic differentiates two different conditions. normal wake up normal wake up can occur when the lin transceiver was set in standby mode while lin was in recessive (high) state. a dominant level at lin for t linbus , switches the L99PM72PXP to active mode. wake up from short to gnd condition if the lin transceiver was set in standby mode while lin was in dominant (low) state, recessive level at lin for t linbus , switchs the L99PM72PXP to active mode. note: a wake up caused by a message on the bus starts the voltage regulator and the microcontroller to switch the application back to normal operation mode. 2.8.3 lin pull-up the master node pull-up resistor (1 k ? ) can be connected to v s using the internal lin_pu high side switch. this high side switch can be controlled by spi in order to allow disconnection of the pull-up resistor in case of lin bus short to gnd conditions. figure 18. master node configuration using lin_pu (optional) c o n t r o l 6 s , ) . c o n t r o l k , ) . ' n d k - a s t e r n o d e p u l l u p , ) . 0 5 4 3 7 ! ' 6 detailed description L99PM72PXP 34/128 doc id 023553 rev 3 lin_pu high side driver characteristics: activated by default and can be turned off by spi command (cr4) remains active in standby modes switch off only in case of over-temperature (tsd2 = thermal shut down #2) no over current protection. typical r ds(on) , 10 ? 2.9 high speed can bus transceiver general requirements: communication speed up to 1mbit/s. iso 11898-2 and iso 11898-5 compliant selective wake-up functionality according to iso 11898-6 non-selective wake-up functionality according to iso 11898-5 sae j2284 compliant function range from -27 v to 40 v dc at can pins. gnd disconnection fail safe at module level. gnd shift operation at system level. microcontroller interface with cmos compatible i/o pins. esd and transient immunity according to iso7637 and en / iec61000-4-2 matched output slopes and propagation delay receive-only mode available for further reducing the current consumption in standby mode, the integrated can bus interface offers an ultra-low current consumption. L99PM72PXP detailed description doc id 023553 rev 3 35/128 2.9.1 can transceiver operating modes figure 19. transceiver state diagram if selective wake-up is disabled (cr16 sw_en = 0) 9 % $ 7 6 w d q g e \ 9 6 w d q g e \ $ & 7 , 9 ( 7 5 ; 1 r u p d o & $ 1 7 5 ; 6 7 % < & $ 1 7 5 ; 6 7 % < & $ 1 $ & 7 & $ 1 $ & 7 6 3 , f p g j r 9 % $ 7 v w e \ 6 3 , f p g j r 9 % $ 7 v w e \ 6 3 , f p g j r 9 v w e \ 6 3 , f p g j r 9 v w e \ : d n h x s s d w w h u q : 8 3 r u 6 3 , ) o d j v : $ . ( & $ 1 : 8 3 5 ; 2 ) ) 7 ; 2 ) ) : d n h x s 2 1 5 ; 2 ) ) 7 ; 2 ) ) : d n h x s 2 1 5 ; 2 1 7 ; 2 1 : d n h x s 2 ) ) 5 ; 2 ) ) 7 ; 2 ) ) : d n h x s 2 1 : d n h x s s d w w h u q : 8 3 ) o d j v : $ . ( & $ 1 : 8 3 : d n h x s s d w w h u q : 8 3 ) o d j : 8 3 & $ 1 7 5 ; 6 7 % < ( " 1 ( $ ' 5 detailed description L99PM72PXP 36/128 doc id 023553 rev 3 figure 20. can transceiver state diagram if selective wake-up is enabled (cr16 sw_en = 1) trx normal mode full functionality of the can-transceiver is available (transmitter and receiver) and the bus biasing is enabled. state transitions from 'trx normal' mode to 'v bat_standby ' and 'v 1_standby ' are possible. no interrupt is generated in this mode. can trx_stby mode the can-transmitter is disabled in this mode and the rxdc-pin is kept at high ('recessive') level. if selective wake-up is enabled (sw_en=1), the receiver, can biasing and the reference oscillator are active. once a wake up frame (w uf) is detected by the internal can frame detection logic, this wake-up event is indicated to the micro-controller by an interrupt signal (see section 2.2.5: interrupt for more details). a wake-up pattern (wup) is not required and does not count as a frame error. since a further can-timeout cannot be indicated, if the can_to bit has already been set, it is recommended to clear this bit before entering v 1_standby mode. if selective wake-up is disabled (sw_en = 0), the can-receiver is capable to detect a wake-up pattern (wup). in v 1_standby mode and active mode, a wup is indicated to the micro-controller by an interrupt signal (see section 2.2.5: interrupt for more details). in this 9 % $ 7 6 w d q g e \ 9 6 w d q g e \ $ & 7 , 9 ( 7 5 ; 1 r u p d o & $ 1 7 5 ; 6 7 % < & $ 1 7 5 ; 6 7 % < & $ 1 $ & 7 & $ 1 $ & 7 7 5 ; 6 / ( ( 3 6 3 , f p g j r 9 % $ 7 v w e \ 3 1 7 5 ; v h o h f w l y h 6 / ( ( 3 : d n h x s s d w w h u q : 8 3 & $ 1 & r p x q l f d w l r q 7 l p h r x w ) o d j & $ 1 7 2 6 3 , f p g j r 9 % $ 7 v w e \ 6 3 , f p g j r 9 v w e \ 6 3 , f p g j r 9 v w e \ : d n h x s ) u d p h : 8 ) ) o d j v : 8 3 : 8 ) : $ . ( & $ 1 r u 6 3 , f p g 5 ; 2 ) ) 7 ; 2 ) ) : d n h x s 2 1 5 ; 2 ) ) 7 ; 2 ) ) : d n h x s 2 1 5 ; 2 1 7 ; 2 1 : d n h x s 2 ) ) 5 ; 2 ) ) 7 ; 2 ) ) : d n h x s 2 ) ) 5 ; 2 ) ) 7 ; 2 ) ) : d n h x s 2 1 : d n h x s ) u d p h : 8 ) ) o d j v : 8 3 : 8 ) : $ . ( & $ 1 r u ) u d p h ' h w h f w l r q ( u u r u ) o d j ) ' ( u u : d n h x s i u d p h : 8 ) ) o d j v : 8 3 : 8 ) ( " 1 ( $ ' 5 L99PM72PXP detailed description doc id 023553 rev 3 37/128 mode (sw_en = 0) the automatic voltage biasing is disabled and the transceiver biasing works according to iso 11898-5. there is no automatic state transition into trx normal mode in case of a detected can wake-up (wuf or wup). after serving the interrupt the micro controller can initiate a state transition into trx normal mode by setting the spi bit can_act to '1'. trx_sleep (sw_en=1) the can and lin transceivers are disabled. th e can selective wakeup reference oscillator is off, while the receiver is in low power mode. after the detection of can communication (wup), the transceiver enters 'pn_trx_selective_sleep' mode, starts the oscillator and de codes the can frame. 'trx_sleep' mode is ente red automatically after a can communication timeout. pn trx selective sleep (sw_en=1) in this mode the can frame detection logic is enabled (receiver an d reference oscillator enabled). in case of receiving a wake up frame (wuf) a state transition to 'can trx_stby' is done. after the biasing has been switched on, not more than four can frames are ignored before a wake-up frame is recognized and the device wakes up. if there is no can communication and the can bus is recessive for longer than t silence , an automatic state tr ansition to 'trx_sleep' is done. in case of a frame-detect-error (sr4, fderr=1), an automatic wake up is performed and the selective wakeup feature is disabled (sw_en=0). 2.9.2 sequence for enabli ng selective wakeup after power-on reset the selective wakeup feature is disabled. the configuration registers 7 to 15 have to be read and verified by the microcontroller in order to ensure a valid configuration. a read operation to registers 7 to 15 is required to allow enabling the selective wake-up feature (set sw_en=1). a valid read operation is indicated by the sw_rdxx bits in sr 4. the sw_rdxx bits are reset to 0 with every write operation. when all sw_rd bits are set, the sw_en bit in cr 16 can be set to enable the selective wakeup function. in case the syserror bit in sr 4 is set while selective wakeup is enabled, the selective wakeup is automatic ally disabled. in case syserror is set, enabling the selective wakeup function is prohibited. 2.9.3 can error handling the L99PM72PXP provides the followin g four error handling features. after power-on reset (v s >v por ) the can transceiver is disabled. the transceiver is enabled by setting the can_act bit in control register 4. detailed description L99PM72PXP 38/128 doc id 023553 rev 3 the can transmitter is disabled automatically in case of the following errors: dominant txdc time out can permanent recessive rxdc permanent recessive thermal shutdown 1 the can receiver is not disabled in case of any failure condition. dominant txdc time out if txdc is in dominant state (low) for t > t dom(txd) the transmitter is disabled, status bit is latched and can be read and optionally cleared by spi. the transmitter remains disabled until the status register is cleared. can permanent recessive if txdc changes to dominant (low) state but can bus does not follow for 4 times, the transmitter is disabled, status bit is latched and can be read and optionally cleared by spi. the transmitter remains disabled until the status register is cleared. can permanent dominant if the bus state is dominant (low) for t > t can a permanent dominant status is detected. the status bit is latched and can be read and optionally cleared by spi. the transmitter is not disabled. rxdc permanent recessive if rxdc pin is clamped to recessive (high) state, the controller is not able to recognize a bus dominant state and could start messages at any time, which results in disturbing the overall bus communication. therefore, if rxdc does no t follow txdc for 4 times the transmitter is disabled. the status bit is latched and can be read and optionally cleared by spi. the transmitter remains disabled until the status register is cleared. 2.9.4 wake up by can the L99PM72PXP supports 2 wakeup modes. the selective wakeup according to iso 11898-6 or the wakeup by any bus activity according to iso 11898-2/-5. the wake up behavior can be configured by spi (see chapter 6: st spi ). wake up by can pattern (wup) the default setting for the wake up behavior after power-on reset is the wake up by regular communication on the can bus. when the can transceiver is in a standby mode (can trx_stby or trx_sleep) the device can be woken up by sending two consecutive dominant bits separated by a recessive bit. normal pattern wake up can occur when can pattern wake up option is enabled and the can transceiver was set in standby mode (can trx_stby or trx_sleep) while can L99PM72PXP detailed description doc id 023553 rev 3 39/128 bus was in recessive (high) state or dominant (low) state. in order to wake up the L99PM72PXP, the following cr iteria must be fulfilled: the can interface wake-up receiver must receive a series of two consecutive valid dominant pulses, each of which must be longer than 2 s the distance between 2 pulses must be longer than 2 s. the two pulses must occur within a time frame of 1.0 ms note: a wake up caused by a message on the bus starts the voltage regulator and the microcontroller to switch the application back to normal operation mode. figure 21. can wake up capabilities note: pictures above illustrate t he wake up behaviour from v 1_standby mode. for wake up from v bat_standby mode the nreset signal (with 2 ms ti ming) is generated instead of the rxdl(interrupt) signal. wakeup by can frame (wuf) wake from can trx_stby if the can transceiver is in stby the can frame detection logic is active. in case of a valid wake up frame the interrupt on pin rxdc is generated and the wuf flag for wake up identification is set. there is no automatic state transition from can transceiver point of view. after serving the interrupt the micro can bring the can transceiver into trx_normal by setting can_act = 1 (cr 4). wake up from trx_sleep if the can transceiver is in trx_sleep mode the can frame detection logic is disabled. the wake up can be done in two steps. to enable the can frame detection logic a wake up 3 d w w h u q : d n h x s $ & 7 , 9 ( 6 7 $ 1 ' % < $ & 7 , 9 ( & $ 1 5 ; 6 7 $ 7 ( ! x v ! x v ! x v p v 6 w d q g d u g f d q s d w w h u q z d n h x s $ & 7 , 9 ( 6 7 $ 1 ' % < $ & 7 , 9 ( & $ 1 5 ; 6 7 $ 7 ( ! x v ! x v ! x v p v & $ 1 s d w w h u q z d n h x s z l w k g r p l q d q w e h i r u h 6 w d q g e \ ( " 1 ( $ ' 5 detailed description L99PM72PXP 40/128 doc id 023553 rev 3 pattern must be sent on the bus. with the detection of the wake up pattern an automatic state transition to ?pn_trx_selective_sleep? state is done. wup flag is set. in ?pn_trx_selective_sleep? the can frame detection logic is enabled. if a valid wake up frame is detected a state transition to trx_stby is done, the wuf flag is set and the micro is powered up. the remote transition request bit is ignored in wake-up frames. also masking of the data length code (dlc) bits is not supported. after expiration of the frame error counter (fec), and if the erroneous frame leading to the fec-overflow is long enough to contain a crc-field, a wake up is performed and the selective wakeup feature is disabled. if the frame is shorter the fec starts again from 0 without having set the fd_err-flag and without wake-up. the frame-error-counter (fec) is cleared after each expiration of the time t silence whenever the frame detection logic is enabled. ringing on the dominant-to-recessive edge of the can-signal is filtered up to 50% of the can-bit-time. 2.9.5 can receive only mode with the can_rec_only bit in control register 4 it is possible to disable the can transmitter in active mode. in this mode it is possible to listen to the bus but not sending to it. the receiver termination network is still activated in this mode. 2.9.6 can looping mode if the can_loop_en bit in control register 4 is set the txdc input is mapped directly to the rxdc pin. this mode can be used in combination with the can receive only mode, to run diagnosis for the can protocol handler of the micro controller. 2.10 serial peripheral interface (st spi standard 3.0) a 24 bit spi is used for bi-directional communication with the micro controller. during active mode, the spi triggers the watchdog controls the modes and status of all l 99pm72pxp modules (incl. input and output drivers) provides driver output diagnostic provide L99PM72PXP diagnosti c (incl. over temperat ure warning, L99PM72PXP operation status) the spi can be driven by a micro controller with its spi peripheral running in following mode: cpol = 0 and cpha = 0. for this mode input data is sampled by the low to high transition of the clock clk, and output data is changed from the high to low transition of clk. this device is not limited to micro controlle r with a built-in spi. only three cmos-compatible output pins and one input pin are needed to communicate with the device. a fault condition can be detected by setting csn to low. if csn = 0, the do pin reflects the global error flag (fault condition) of the device. L99PM72PXP detailed description doc id 023553 rev 3 41/128 chip select not (csn) the input pin is used to select the serial interface of this device. when csn is high, the output pin (do) is in high impedance state. a low signal activates the output driver and a serial communication can be started. the state during csn = 0 is called a communication frame. if csn = low for t > t csnfail the do output is switched to high impedance in order to not block the signal line for other spi nodes. serial data in (di) the input pin is used to transfer data serial into the device. the data applied to the di are sampled at the rising edge of the clk signal and shifted into an internal 24 bit shift register. at the rising edge of the csn signal the contents of the shift register is transferred to data input register. the writing to the selected data input register is only enabled if exactly 24 bits are transmitted within one communication fr ame (i.e. csn low). if more or less clock pulses are counted within one frame the complete frame is ignored. this safety function is implemented to avoid an activation of the output stages by a wrong communication frame. note: due to this safety functionality a daisy chai ning of spi is not possible. instead, a parallel operation of the spi bus by controlling th e csn signal of the connected ic's is recommended. serial data out (do) the data output driver is activated by a logical low level at the csn input and goes from high impedance to a low or high level depending on the global error flag (fault condition). the first rising edge of the clk input after a high to low transition of the csn pin transfers the content of the selected status register into the data out shift register. each subsequent falling edge of the clk sh ifts the next bit out. serial clock (clk) the clk input is used to synchronize the input and output serial bit streams. the data input (di) is sampled at the rising edge of the clk and the data output (do) changes with the falling edge of the clk signal. the spi can be driven with a clk frequency up to 1 mhz. protection and diagnosis L99PM72PXP 42/128 doc id 023553 rev 3 3 protection and diagnosis 3.1 power supply fail overvoltage and undervoltage detection on v s 3.1.1 v s overvoltage if the supply voltage v s reaches the over voltage threshold (v sov ): outputs outx, relx and lin are switched to high impedance state (load protection). can is not disabled. recovery of outputs when the overvoltage condition disappears is depending on the setting of vlock_out_en bit in control register 4. ? vlock_out_en = 1: outputs are off until read and clear sr3. ? vlock_out_en = 0: outputs switch automatically on when overvoltage condition disappears. the over voltage bit is set and can be cleared with a ?read and clear? command. the overvoltage bit is removed automatically if vlock_out_en = 0 and the overvoltage condition disappears. outputs rel1,2 can be excluded from a shutdown in case of overvoltage by spi (ls_ov/uv_shutdown_en in cr4) 3.1.2 v s undervoltage if the supply voltage v s drops below the under voltage threshold voltage (v suv ) outputs outx, relx and lin are switched to high impedance state (load protection). can is not disabled. recovery of outputs when the undervoltage condition disappears is depending on the setting of vlock_out_en bit. ? vlock_out_en = 1: outputs are off until read and clear sr3. ? vlock_out_en = 0: outputs switch on automatically when undervoltage condition disappears. the undervoltage bit is set and can be cleared with a ?read and clear? command. the undervoltage bit is removed automatically if vlock_out_en = 0 and the undervoltage condition disappears outputs rel1,2 can be excluded from a shutdown in case of undervoltage by spi (ls_ov/uv_shutdown_en in cr4) L99PM72PXP protection and diagnosis doc id 023553 rev 3 43/128 figure 22. overvoltage and undervoltage protection and diagnosis $ f w l y h 0 r g h 6 w d q g e \ 0 r g h v g x u l q j f \ f o l f v h q v h 9 v 8 y h u y r o w d j h 6 k x w g r z q $ o o r x w s x w v k l j k , p s h g d q f h h [ f h s w 5 ( / r x w s x w v l i / 6 b r y x y ' l d j q r v l v 8 9 9 v 2 y h u y r o w d j h 6 k x w g r z q $ o o r x w s x w v k l j k , p s h g d q f h h [ f h s w 5 ( / r x w s x w v l i / 6 b r y x y ' l d j q r v l v 2 9 9 v 2 y h u y r o w d j h 9 v ! 9 v r y 9 v 8 q g h u y r o w d j h 9 v 9 v x y 9 v 9 v r y $ 1 ' ? 5 h d g d q g & o h d u ? 2 5 9 v 9 v r y $ 1 ' 9 o r f n r x w 9 v ! 9 v x y $ 1 ' ? 5 h d g d q g & o h d u ? 2 5 9 v ! 9 v x y $ 1 ' 9 o r f n r x w $ * 9 protection and diagnosis L99PM72PXP 44/128 doc id 023553 rev 3 3.2 temperature warning and thermal shut-down figure 23. thermal shutdown protection and diagnosis note: the thermal state machine recovers the same state were it was before entering standby mode. in case of a tsd2 it enters tsd1 state. $ f w l y h 0 r g h 6 w d q g e \ 0 r g h v g x u l q j f \ f o l f v h q v h 7 h p s h u d w x u h : d u q l q j ' l d j q r v l v 7 : 7 6 ' $ o o r x w s x w v h [ f h s w 9 r i i ' l d j q r v l v 7 6 ' 7 m ! 7 6 ' ? 5 h d g d q g & o h d u ? 2 5 3 r z h u r q u h v h w 7 6 ' $ o o r x w s x w v r i i 9 r i i i r u v h f ' l d j q r v l v 7 6 ' 7 m ! 7 6 ' 9 e d w v w e \ $ o o r x w s x w v l q f o 9 r i i [ 7 6 ' : d n h x s h y h q w 3 r z h u r q u h v h w ? 5 h d g d q g & o h d u ? 2 5 3 r z h u r q u h v h w 7 m ! 7 z 7 ! v h f 3 r z h u 2 q 5 h v h w $ o o r x w s x w v l q f o 9 r i i 9 v ! 9 s r u $ * 9 L99PM72PXP protection and diagnosis doc id 023553 rev 3 45/128 3.3 high side driver outputs the component provides a total of 4 high side outputs out1...4, (7 ? typ. at 25c) to drive e.g. led's or hall sensors and 1 high side output out_hs with 1 ? typ. at 25c). the high side outputs switch off in case of: v s overvoltage and undervoltage overcurrent overtemperature (tsd1) with pre warning (c) in case of overcurrent or overtemperature (tsd1) condition, the drivers switch off. the according status bit is latched and can be read and optionally cleared by spi. the drivers remain off until the status is cleared. in case overvoltage or undervoltage condition, the drivers are switched off. the according status bit is latched and can be read and optionally cleared by spi. if the vlock_out_en bit (control register 4) is set to ?1? the drivers remain off until the status is cleared. if the vlock_out_en bit is set to ?0? the drivers switch on automatically if the error condition disappears. in case of open load condition, the according status register is latched. the status can be read and optionally cleared by spi. the high sides are not switched off. for out_hs the auto recovery feature (ouths_rec_en bit control register 4) can be enabled. if this bit is set to ?1? the driver automatically restarts from a overload condition. this overload recovery feature is intended for loads which have an initial current higher than the over current limit of the output (e.g. inrush current of cold light bulbs). during auto recovery mode the over current status bit can not be read from spi. the device itself cannot distinguish between a real overload and a non linear load like a light bulb. a real overload condition can only be qualified by time. as an example, the micro controller can switch on light bulbs by setting the over current recovery bit for the first 50 ms. after clearing the recovery bit, the output is automatically disabled if the overload condition still exists. in case of a fail safe condition, the high side drivers are switched off. the control bits are set to default values. (except out3/fso if it is used as a high side driver output) note: the maximum voltage and current applied to the high side outputs is specified in 2.1 ?absolute maximum ratings?. appropriate external protection may be required in order to respect these limits under application conditions. each high side driver can be driven whether with a pwm signal or with a internal timer (see ta bl e 8 ). for more details please refer to section 6.2.3: control register 1 c. except out3 when configured as fso table 8. pwm configuration for high-side outputs high side output pwm channel internal timer out1 pwm 1 timer 1 out2 pwm 2 timer 2 protection and diagnosis L99PM72PXP 46/128 doc id 023553 rev 3 the pwm 1/3 channels start a pwm period with the on phase, while the pwm 2/4 channels start with the off phase. in this way it is possible to use the 4 pwm channels in a phase shifted way. the picture below shows this feature with a duty cycle of 25% for both pwm channels. figure 24. phase shifted pwm 3.4 low side driver outputs rel1, rel2 the outputs rel1, rel2 (r dson =2 ? typ. @25 ? c) are specially designed to drive relay loads. the outputs provide an active output zener clamping (45 v typ.) feature for the demagnetization of the relay coil, even though a load dump condition exists. for fail_safe reasons the relay dr ivers are linked with the fail safe operation: in case of entering the fail safe mode, the relay drivers switch off and the spi control bits are set to default (i.e. driver is off). the low side drivers switch off in case of: v s overvoltage and undervoltage overcurrent overtemperature with pre warning out3 pwm 3 - out4 pwm 4 timer 2 ouths pwm 3 / pwm 4 timer 1 / timer 2 table 8. pwm configuration for high-side outputs (continued) high side output pwm channel internal timer 3 : 0 3 h u l r g 2 8 7 3 : 0 [ ) 2 8 7 3 : 0 [ ) $ * 9 L99PM72PXP protection and diagnosis doc id 023553 rev 3 47/128 in case of overload or overtemperature (tsd1) condition, the drivers switch off. the according status bit is latched and can be read and optionally cleared by spi. the drivers remain off until the status is cleared. in case v s overvoltage or undervoltage condition, the drivers are switched off. the according status bit is latched and can be read and optionally cleared by spi. if the vlock_out_en bit (control register 4) is set to ?1? the drivers remain off until the status is cleared. if the vlock_out_en bit is set to ?0? the drivers are switched on automatically if the error condition disappears. with the ls_ov/uv_shutdown_en bit (control register 4) the drivers can be excluded from a switch off in case of v s overvoltage or undervoltage. if the bit is set to ?1? the driver switches off, otherwise the drivers remain on. 3.5 spi diagnosis digital diagnosis features are provided by spi (for details please refer to section 6.2: spi registers ) v 1 reset threshold programmable overtemperature including. pre warning open load separately for each output stage except rel1/rel2 overload status separately for each output stage v s -supply overvoltage/undervoltage v 1 and v 2 fail bit v 2 output short to gnd status of the wu1...3 wake-up sources (can, lin, spi, timer, wu1?3) chip reset bit (start from power-on reset) number of unsuccessful v 1 restarts after thermal shutdown number of sequential watchdog failures lin diagnosis (permanent recessive/dominant, dominant txd) can diagnosis (permanent recessive/do minant, dominant txd, recessive rxd) device state (wake-up from v 1_standby or v bat_standby ) forced v bat_standby after wd-fail, forced v bat_standby after overtemperature watchdog timer state (diagnosis of watchdog) failsafe status spi communication error diagnosis of selective wake functionality according to iso 11898-6 typical application L99PM72PXP 48/128 doc id 023553 rev 3 4 typical application figure 25. typical application diagram 1. in case a lin/can conformance test has to be ex ecuted on the device, some capacitances have to be placed on the fixed-function-unit pins: - 22 nf (low esr and close to the pin) for all power outputs (out_hs, out1 ? 4, rel1 and rel2) and also for the wake-up inputs, if they go out of the pcb. - 47 f and a 100 nf low esr capacitance (clo se to the pin) at the power supply v s . ' , + l j k 6 l g h 6 3 , / 2 * , & : l q g r z : d w f k g r j 9 v $ * 1 ' 9 : 8 & 6 1 & / . ' 2 2 8 7 b + 6 2 8 7 5 ( / 5 ( / : d n h 8 s , 1 + l j k 6 l g h / r z 6 l g h 2 x w s x w & o d p s 9 r o w d j h 0 r q l w r u : d n h 8 s , 1 : 8 7 h p s 3 u h z d u q l q j 6 k x w g r z q 8 q g h u y r o w d j h 2 y h u y r o w d j h 6 k x w g r z q / r z 6 l g h 2 x w s x w & o d p s 0 9 v 9 e d w & \ f o l f & r q w d f w 0 r q l w r u l q j 0 l f u r f r q w u r o o h u 9 e d w / , 1 5 [ ' / 1 , 1 7 7 [ ' / 1 5 ( 6 ( 7 9 r o w d j h 5 h j x o d w r u q ) 9 q ) 9 v : d n h 8 s , 1 : 8 + l j k 6 l g h + l j k 6 l g h + l j k 6 l g h / , 1 / , 1 3 8 2 3 2 3 2 3 b 2 8 7 ? & $ ' & / , 1 h j % x o e / ( ' + d o o 6 h q v r u 3 * 1 ' + 6 & $ 1 & $ 1 / 1 & & $ 1 + & $ 1 6 8 3 & $ 1 7 [ ' & 5 [ ' & 1 , 1 7 ( [ w h u q d o ) d l o 6 d i h / r j l f 9 ( [ w h u q d o o r d g v 9 v 9 r o w d j h 5 h j x o d w r u / , 1 f r p s o l d q w 6 $ ( - f r p s d w l e o h , 6 2 d q g 6 $ ( - f r p s o l d q w 2 3 2 3 2 3 b 2 8 7 2 8 7 2 8 7 ) 6 2 2 8 7 h j / ( ' + d o o 6 h q v r u ( " 1 ( $ ' 5 L99PM72PXP electrical specifications doc id 023553 rev 3 49/128 5 electrical specifications 5.1 absolute maximum ratings all maximum ratings are absolute ratings. leaving the limitation of any of these values may cause an irreversible damage of the integrated circuit. loss of ground or ground shift with externally grounded loads: esd structures are configured for nominal currents only. if external loads are connected to different grounds, the current load must be limited to this nominal current. table 9. absolute maximum ratings symbol parameter / test condition value [dc voltage] unit v s dc supply voltage / ?jump start? -0.3 to +28 v load dump -0.3 to +40 v v 1 stabilized supply voltage, logic supply -0.3 to (v 1 +0.3) v 1 L99PM72PXP electrical specifications doc id 023553 rev 3 51/128 figure 26. thermal data of powersso-36 pad soldered 0 5 10 15 20 25 30 35 0.0001 0.001 0.01 0.1 1 10 100 1000 time (s) zth (oc/w) powersso-36 on 2s2p powersso-36 on 2s2p th. enh. pad soldered 0 5 10 15 20 25 30 35 0.0001 0.001 0.01 0.1 1 10 100 1000 time (s) zth (oc/w) powersso-36 on 2s2p powersso-36 on 2s2p th. enh. a g00022v1 electrical specifications L99PM72PXP 52/128 doc id 023553 rev 3 5.4 package and pcb thermal data 5.4.1 powersso-36 thermal data figure 27. powersso-36 pc board note: layout condition of r th and z th measurements (board finish thickness 1.6 mm +/- 10% board double layer, board dimension 129x60, board material fr4, cu thickness 0.070 mm (front and back side), thermal vias separation 1.2 mm, thermal via diameter 0.3 mm +/- 0.08 mm, cu thickness on vias 0.025 mm). $ * 9 L99PM72PXP electrical specifications doc id 023553 rev 3 53/128 figure 28. powersso-36 thermal resistance juncti on to ambient vs pcb copper area (v 1 on) figure 29. powersso-36 thermal impedance junction to ambient vs pcb copper area (single pulse with v 1 on) 5 7 + m d p e 5 7 + m d p e 5 7 + m b d p e & : 3 & % & x k h d w v l q n d u h d f p a $ * 9 100 zth (c/w) cu=8 cm2 cu=2 cm 2 10 100 zth (c/w) cu=8 cm2 cu=2 cm2 cu=foot print 10 100 zth (c/w) cu=8 cm2 cu=2 cm2 cu=foot print 1 10 100 0.01 0.1 1 10 100 1000 zth (c/w) time ( s ) cu=8 cm2 cu=2 cm2 cu=foot print 1 10 100 0.01 0.1 1 10 100 1000 zth (c/w) time (s) cu=8 cm2 cu=2 cm2 cu=foot print a g00025v1 electrical specifications L99PM72PXP 54/128 doc id 023553 rev 3 figure 30. powersso-36 thermal fitting model (v 1 on) equation 1: pulse calculation formula table 13. thermal parameter area/island (cm 2 )footprint28 r1 (c/w) 2 r2 (c/w) 8 4 4 r3 (c/w) 20 15.5 10 r4 (c/w) 36 29 18 c1 (w.s/c) 0.01 c2 (w.s/c) 0.1 0.2 0.2 c3 (w.s/c) 0.8 1 1.5 c4 (w.s/c) 2 3 6 $ * 9 z th ? r th ? z thtp 1 ? ? ?? + ? = where ? t p t ? = L99PM72PXP electrical specifications doc id 023553 rev 3 55/128 5.5 electrical characteristics 5.5.1 supply and supply monitoring the voltages are referred to ground and currents are assumed positive, when the current flows into the pin. t j = -40c to 130c, unless otherwise specified. table 14. supply and supply monitoring symbol parameter test condition min. typ. max. unit v suv v s undervoltage threshold v s increasing / decreasing 5.11 5.81 v v hyst_uv v s undervoltage hysteresis 0.04 0.1 0.15 v v sov v s overvoltage threshold v s increasing / decreasing 18.5 22 v v hyst_ov v s overvoltage hysteresis hysteresis 0.5 1 1.5 v t ovuv_filt v s overvoltage /undervoltage filter time 64*t osc i v(act) current consumption in active mode v s =12v; txdc=high; txdl = high; v 1 =on; v 2 = on; hs/ls driver off 612ma i v(bat) current consumption in v bat_standby mode (1) 1. conditions for specifi ed current consumption: v lin >(v s -1.5v) (can_h ? can_l) < 0.4 v or (can_h ? can_l) > 1.2 v v wu <1v or v wu > (vs ? 1.5v) the current consumption in standby modes with cyclic sense can be calcul ated using the following formulas: i v(bat)cs =i v(bat) +55a+(2ma*(t on + 100 s) / t) i( v1)cs =i v1 + 55 a + (2 ma * (t on + 100 s) / t) v s = 12v; both voltage regulators deactivated; hs/ls driver off; no can communication 81228a i v(bat)cs current consumption in v bat_standby mode with cyclic sense enabled (1) v s = 12 v; both voltage regulators deactivated; t=50ms; t on = 100 s 40 75 125 a i v(bat)cw current consumption in v bat_standby mode with cyclic wake enabled (1) v s = 12 v; both voltage regulators deactivated during standby phase 40 75 125 a i v(v1stby) current consumption in v 1_standby mode (1) v s = 12 v; voltage regulator v 1 active (i v1 electrical specifications L99PM72PXP 56/128 doc id 023553 rev 3 5.5.2 oscillator the voltages are referred to ground and currents are assumed positive, when the current flows into the pin. 4.5 v < v s < 28 v; t j = -40c to 130c, unless otherwise specified. all outputs open; t j = -40c to 130c, unless otherwise specified. 5.5.3 power-on reset (v s ) 5.5.4 voltage regulator v 1 the voltages are referred to ground and currents are assumed positive, when the current flows into the pin. 4.5 v < v s < 28 v; t j = -40c to 130c, unless otherwise specified. table 15. oscillator symbol parameter test condition min. typ. max. unit f clk oscillation frequency 0.80 1.0 1.35 mhz table 16. power-on reset (v s ) symbol parameter test condition min. typ. max. unit v por v por threshold v s increasing 3.45 4.5 v v s decreasing (1) 1. this threshold is valid if v s had already reached 7 v previously. 2.35 3.5 v table 17. voltage regulator v 1 symbol parameter test condition min. typ. max. unit v 1 output voltage 5.0 v output voltage tolerance active mode i load = 4 ma to 100 ma; v s =13.5v -2 2 % v hc1 output voltage tolerance; active mode; high current i load = 100 ma to 250 ma; v s =13.5v -3 3 % i load =250ma; v s =13.5v -5 5 % v stb1 output voltage tolerance v 1_standby mode i load = 0 a to 4 ma; v s =13.5v -2 4 % v dp1 drop-out voltage i load =50ma; v s =5v 0.2 0.4 v i load =100ma; v s =4.5v 0.2 0.5 v i load =100ma; v s =5v 0.3 0.5 v i load = 150 ma; v s = 4.5 v 0.45 0.6 v i load = 150 ma; v s = 5.0 v 0.45 0.6 v i cc1 output current in active mode max. continuous load current 250 ma i ccmax1 short circuit output current current limitation 340 600 900 ma L99PM72PXP electrical specifications doc id 023553 rev 3 57/128 5.5.5 voltage regulator v 2 the voltages are referred to ground and currents are assumed positive, when the current flows into the pin. 4.5 v < v s < 28 v; t j = -40c to 130c, unless otherwise specified. c load1 load capacitor 1 ceramic (+/- 20%) 0.22 (1) f t tsd v 1 deactivation time after thermal shutdown 1sec i cmp_ris current comp. rising threshold rising current 1.0 2.5 4.0 ma i cmp_fal current comp. falling threshold falling current 0.8 1.95 3.1 ma i cmp_hys current comp. hysteresis 0.5 ma v 1fail v 1 fail threshold v 1 forced 2 v t v1fail v 1 fail filter time 2 s t v1short v 1 short filter time 4 ms 1. nominal capacitor value required fo r stability of the regulator. test ed with 220nf ceramic (+/- 20%). capacitor must be located close to the regulator output pin. table 17. voltage regulator v 1 (continued) symbol parameter test condition min. typ. max. unit table 18. voltage regulator v 2 symbol parameter test condition min. typ. max. unit v 2 output voltage 5.0 v v 2 output voltage tolerance; active mode i load = 1 ma to 50 ma; v s =13.5v -3 3 % v hc1 output voltage tolerance; active mode i load = 50 ma to 80 ma; v s =13.5v -4 4 % v 2 output voltage tolerance; active mode; high current i load =100ma; v s =13.5v -6 6 % v stb2 output voltage tolerance v 1_standby mode i load =1ma; v s = 13.5 v -6.5 6.5 % v dp2 drop-out voltage i load =25ma; v s = 5.25 v 0.3 0.4 v i load =50ma; v s =5.25v 0.4 0.7 v i cc2 output current in active mode max. continuous load current 100 ma i ccmax2 short circuit output current current limitation 150 280 450 ma c load load capacitor ceramic (+/- 20%) 0.22 (1) f v 2fail v 2 fail threshold v 2 forced 2 v electrical specifications L99PM72PXP 58/128 doc id 023553 rev 3 5.5.6 reset output the voltages are referred to gnd and currents are assumed positive, when the current flows into the pin. 4.0 v < v s < 28 v; t j = -40c to 130c, unless otherwise specified. 5.5.7 watchdog 4.5 v < v s <28v; 4.8v L99PM72PXP electrical specifications doc id 023553 rev 3 59/128 figure 31. watchdog timing (long, early, late and safe window) t lfw3 late failure window 3 200 ms t sw3 safe window 3 75 120 ms t efw4 early failure window 4 90 ms t lfw4 late failure window 4 400 ms t sw4 safe window 4 150 240 ms table 20. watchdog (continued) symbol parameter test condition min. typ. max. unit 4 , 7 l o n g w i n d o w m s 4 # 7 c l o s e d w i n d o w m s 4 / 7 o p e n w i n d o w m s t r i g g e r s i g n a l 4 7 $ 2 w a t c h d o g r e s e t m s t i m e m s t i m e m s t i m e m s . o r m a l s t a r t u p o p e r a t i o n a n d t i m e o u t f a i l u r e s 7 $ t r i g g e r c o r r e c t t r i g g e r t i m i n g 4 , 7 4 # 7 4 / 7 - i s s i n g u # t r i g g e r s i g n a l 4 # 7 4 # 7 4 / 7 . 2 % 3 / u t 4 7 $ 2 4 , 7 e a r l y t r i g g e r t i m i n g m i s s i n g t r i g g e r 4 , 7 4 7 $ 2 n o r m a l o p e r a t i o n m i s s i n g t r i g g e r e a r l y w r i t e 4 , 7 . 2 % 3 / u t 4 7 $ 2 4 7 $ 2 7 $ t r i g g e r 4 , 7 4 , 7 4 7 $ 2 t i m e m s ( " 1 ( $ ' 5 electrical specifications L99PM72PXP 60/128 doc id 023553 rev 3 figure 32. watchdog early, late and safe windows 5.5.8 high side outputs the voltages are referred to gnd and currents are assumed positive, when the current flows into the pin. 6 v < v s < 18 v; 4.8 v < v 1 < 5.2 v; t j = -40c to 130c, unless otherwise specified. s a f e t r i g g e r a r e a 4 % & 7 n ? m a x 4 3 7 n ? m i n 4 , & 7 n ? m i n 4 3 7 n 3 a f e w i n d o w 4 % & 7 n % a r l y & a i l u r e w i n d o w 4 , & 7 n , a t e f a i l u r e w i n d o w t i m e % a r l y 7 a t c h d o g f a i l u r e u n d e f i n e d u n d e f i n e d 4 3 7 n ? m a x , a t e w a t c h d o g f a i l u r e ' ! 0 ' # & 4 table 21. output (out_hs) symbol parameter test condition min. typ. max. unit r ds(on) static drain source on- resistance (i out_hs =150ma) t j =25c 1.0 2.0 ? t j =125c 1.6 3 ? t d(on) switch on delay time 0.2 v s 53560s t d(off) switch off delay time 0.8 v s 40 95 150 s t scf short circuit filter time tested by scan chain 64 * t osc t d_arhs auto recovery filter time tested by scan chain 400 * t osc dv out /dt slew rate 0.18 0.5 0.8 v/s i out short circuit shut down current 480 900 1320 ma i old open load detection current 40 80 120 ma t oldt open load detection time tested by scan chain 64 * t osc i fw (1) 1. parameter guaranteed by design. loss of gnd current (esd structure) 100 ma L99PM72PXP electrical specifications doc id 023553 rev 3 61/128 5.5.9 relay drivers the voltages are referred to gnd and currents are assumed positive, when the current flows into the pin. 6 v < v s < 18 v; 4.8 v < v 1 < 5.2 v; t j = -40 to 130c, unless otherwise specified. table 22. outputs (out1...4) symbol parameter test condition min. typ. max. unit r ds(on) static drain source on- resistance (i out_hs =150ma) i load =60ma; t j = 25c 7 13 ? i out short circuit shut down current 8v L99PM72PXP electrical specifications doc id 023553 rev 3 63/128 table 27. can receive data output: pin rxdc symbol parameter test condition min. typ. max. unit v rxdclow output voltage dominant level active mode, v 1 = 5 v; 2 ma 0.2 0.5 v v rxdchigh output voltage recessive level active mode, v 1 =5v; 2ma 4.5 v table 28. can transmitter and receiver: pins canh and canl symbol parameter test condition min. typ. max. unit v canhdom canh voltage level in dominant state active mode; v txdc =v txdclow ; r l =60 ? ; r l =50 ? 2.75 4.5 v v canldom canl voltage level in dominant state active mode; v txdc =v txdclow ; r l =60 ? ; r l =50 ? 0.5 2.25 v v diff,domout differential output voltage in dominant state: v canhdom - v canldom active mode; v txdc =v txdclow ; r l =60 ? ; r l =50 ? 1.5 3 v v cm driver symmetry: v canhdom +v canldom active mode; v txdc =v txdclow ; r l =60 ? 0.9 * v cansup v cansup 1.1 * v cansup v v canhrec canh voltage level in recessive state (normal mode) active mode; v txdc =v txdchigh ; no load 22.53v v canlrec canl voltage level in recessive state (normal mode) active mode; v txdc =v txdchigh ; no load 22.53v v canhreclp canh voltage level in recessive state (low power mode) v 1_standby mode; v txdc =v txdchigh ; no load -0.1 0 0.1 v v canlreclp canl voltage level in recessive state (low power mode) v 1_standby mode; v txdc =v txdchigh ; no load -0.1 0 0.1 v v diff,recout differential output voltage in recessive state (normal mode): v canhrec -v canlrec active mode; v txdc =v txdchigh ; no load -50 50 mv v diff,recoutlp differential output voltage in recessive state (low power mode): v canhrec - v canlrec v 1_standby mode; v txdc =v txdchigh ; no load -50 50 mv v canhl,cm common mode bus voltage measured with respect to the ground of each can node -12 12 v electrical specifications L99PM72PXP 64/128 doc id 023553 rev 3 i ocanh,dom (0v) canh output current in dominant state active mode; v txdc =v txdclow ; v canh =0v -160 -75 -45 ma i ocanl,dom (5v) canl output current in dominant state active mode; v txdc =v txdclow ; v canl =5v 45 75 160 ma i ocanh,dom (40v) canh output current in dominant state active mode; v txdc =v txdclow ; v canh =40v; v canl =0v; v s =40v 025ma i ocanl,dom (40v) canl output current in dominant state active mode; v txdc =v txdclow ; v canl =40v; v canh =0v; v s =40v 47 75 160 ma i leakage,canh input leakage current unpowered device; v bus =5v; ?v cansupply connect 0 ? to gnd ?v cansupply connect 47 k ? to gnd (1) -10 ? 10 a i leakage,canl input leakage current unpowered device; v bus =5v; ?v cansupply connect 0 ? to gnd ?v cansupply connect 47 k ? to gnd (1) -10 ? 10 a r in internal resistance active mode & v 1- standby mode; v txdc =v txdchigh ; no load 20 27.5 38 k ? r in,matching internal resistor matching canh,canl active mode & v 1_standby mode; v txdc =v txdchigh ; no load; r in(canh) ? r in(canl) 3% r in,diff differential internal resistance active mode & v 1_standby mode; v txdc =v txdchigh ; no load 50 60 75 k ? c in internal capacitance guaranteed by design 20 40 pf c in,diff differential internal capacitance guaranteed by design 10 20 pf table 28. can transmitter and receiv er: pins canh and canl (continued) symbol parameter test condition min. typ. max. unit L99PM72PXP electrical specifications doc id 023553 rev 3 65/128 v thdom differential receiver threshold voltage recessive to dominant state (normal mode) active mode 0.9 v v thdomlp differential receiver threshold voltage recessive to dominant state (low power mode) v 1_standby mode 1.15 v v threc differential receiver threshold voltage dominant to recessive state (normal mode) active mode 0.5 v v threclp differential receiver threshold voltage dominant to recessive state (low power mode) v 1_standby mode 0.4 v 1. guaranteed by design. table 29. can transceiver timing symbol parameter test condition min. typ. max. unit t txpd,hl propagation delay txdc to rxdc (high to low) active mode; r l =120 ? ; c l = 100 pf; c rxdc =15pf; f txdc = 250 khz 255 ns t txpd,lh propagation delay txdc to rxdc (low to high) active mode; r l =120 ? ; c l = 100 pf; c rxdc =15pf; f txdc = 250 khz 255 ns t filter wake up filter time 0.5 5 s t dom(txdc) txdc dominant time- out tested by scan and oscillator 0.8 2 5 ms t can can permanent dominant time-out 700 s t silence can timeout 600 700 1200 ms t bias bias reaction time r l =60 ? ; c l = 100 pf; c gnd = 100 pf 200 s t v1swon v 1 switch-on time after reception of a valid wuf in v bat-standby mode 50 s table 28. can transmitter and receiv er: pins canh and canl (continued) symbol parameter test condition min. typ. max. unit electrical specifications L99PM72PXP 66/128 doc id 023553 rev 3 5.5.12 lin transceiver (e) the voltages are referred to gnd and currents are assumed positive, when the current flows into the pin. 6 v < v s < 18 v; 4.8 v < v 1 < 5.2 v; t junction = -40c to 130 c, unless otherwise specified. e. lin 2.1 compliant for baud rates up to 20 kbit/s. sae j2602 compatible. table 30. lin transmit data input: pin txd symbol parameter test condition min. typ. max. unit v txdlow input voltage dominant level active mode; v 1 = 5 v 1,35 1.8 v v txdhigh input voltage recessive level active mode; v 1 =5v 2.5 3 v v txdhys v txdhigh -v txdlow active mode; v 1 =5v 0.7 1 v r txdpu txd pull up resistor active mode; v 1 =5v 10 20 35 k ? table 31. lin receive data output: pin rxd symbol parameter test condition min. typ. max. unit v rxdlow output voltage dominant level active mode; v 1 = 5 v; 2 ma 0.2 0.5 v v rxdhigh output voltage recessive level active mode; v 1 = 5 v; 2 ma 4.5 v table 32. lin transmitter and receiver: pin lin symbol parameter test condition min. typ. max. unit v thdom receiver threshold voltage recessive to dominant state 0.4 v s 0.45 v s 0.5 v s v v busdom receiver dominant state 0.4 v s v v threc receiver threshold voltage dominant to recessive state 0.5 * v s 0.55 * v s 0.6 * v s v v busrec receiver recessive state 0.6 v s v v thhys receiver threshold hysteresis: v threc - v thdom 0.07 * v s 0.1 * v s 0.175 * v s v v thcnt receiver tolerance center value: (v threc +v thdom )/2 0.475 * v s 0.5 * v s 0.525 * v s v v thwkup receiver wakeup threshold voltage 1.0 1.5 2 v L99PM72PXP electrical specifications doc id 023553 rev 3 67/128 v thwkdwn receiver wakeup threshold voltage v s -3.5 v s -2.5 v s -1.5 v t linbus dominant time for wakeup via bus sleep mode; edge: rec-dom 64 * t osc s i lindomsc transmitter input current limit in dominant state v txd =v txdlow ; v lin =v batmax =18v 40 100 180 ma i bus_pas_dom input leakage current at the receiver incl. pull- up resistor v txd =v txdhigh ; v lin =0v; v bat =12v (1) -1 ma i bus_pas_rec transmitter input current in recessive state in stanby modes; v txd =v txdhigh ; v lin >8v; v bat <18v; v lin ? v bat 20 a i bus_no_gnd input current if loss of gnd at device gnd = v s ; 0 v < v lin <18v; v bat =12v -1 1 ma i bus input current if loss of v bat at device gnd = v s ; 0 v < v lin <18v 100 a v lindom lin voltage level in dominant state active mode; v txd =v txdlow ; i lin =40ma 1.2 v v linrec lin voltage level in recessive state active mode; v txd =v txdhigh ; i lin =10a 0.8 * v s 1v r linup lin output pull up resistor v lin =0v 20 40 60 k ? c lin lin input capacitance 90 pf 1. slave mode. table 33. lin transceiver timing symbol parameter test condition min. typ. max. unit t rxpd receiver propagation delay time t rxpd = max(t rxpdr ,t rxpdf ); t rxpdf = t(0.5 v rxd ) - t(0.45 v lin ); t rxpdr = t(0.5 v rxd )-t(0.55v lin ); v s = 12 v; c rxd = 20 pf; r bus =1k ? ; c bus =1nf; r bus =660 ? ; c bus =6.8nf; r bus =500 ? ; c bus =10nf 6s t rxpd_sym symmetry of receiver propagation delay time (rising vs. falling edge) t rxpd_sym = t rxpdr -t rxpdf ; v s = 12 v; r bus =1k ? ; c bus =1nf; c rxd = 20 pf -2 2 s table 32. lin transmitter and receiver: pin lin (continued) symbol parameter test condition min. typ. max. unit electrical specifications L99PM72PXP 68/128 doc id 023553 rev 3 d1 duty cycle 1 th rec (max) = 0.744 * v s ; th dom (max) = 0.581 * v s ; v s = 7 v to 18 v; t bit = 50 s; d1 = t bus_rec (min) / (2 * t bit ); r bus =1k ? ; c bus = 1nf; r bus =660 ? ; c bus = 6.8 nf; r bus =500 ? ; c bus = 10 nf 0.396 d2 duty cycle 2 th rec (min) = 0.422 * v s ; th dom (min) = 0.284 * v s ; v s = 7.6 v to 18 v; t bit = 50us; d2 = t bus_rec (max) / (2 * t bit ); r bus =1k ? ; c bus = 1nf; r bus =660 ? ; c bus = 6.8 nf; r bus =500 ? ; c bus = 10 nf 0.581 d3 duty cycle 3 th rec (max) = 0.778 * v s ; th dom (max) = 0.616 * v s ; v s = 7vto18v; t bit = 96 s; d3 = t bus_rec (min) / (2 * t bit ); r bus =1k ? ; c bus = 1nf; r bus =660 ? ; c bus = 6.8 nf; r bus =500 ? ; c bus = 10 nf 0.417 d4 duty cycle 4 th rec (min) = 0.389 * v s ; th dom (min) = 0.251 * v s ; v s = 7.6 v to 18 v; t bit = 96 s; d4 = t bus_rec (max) / (2 * t bit ); r bus =1k ? ; c bus = 1nf; r bus =660 ? ; c bus = 6.8 nf; r bus =500 ? ; c bus = 10 nf 0.590 t dom(txdl) txdl dominant time-out 12 ms t lin lin permanent recessive time-out 40 s t dom(bus) lin bus permanent dominant time-out 12 ms table 34. lin pull-up: pin linpu symbol parameter test condition min. typ. max. unit r ds(on) on resistance ? 10.5 16 ? i leak leakage current ? 1 a table 33. lin transceiver timing (continued) symbol parameter test condition min. typ. max. unit L99PM72PXP electrical specifications doc id 023553 rev 3 69/128 figure 33. lin transmit, receive timing 5.5.13 operati onal amplifier the voltages are referred to gnd and currents are assumed positive, when the current flows into the pin. 6 v < v s < 18 v; t j = -40c to 130c, unless otherwise specified. note: the operational amplifie r is on-chip stabilized for external capacitive loads c l < 25pf (all operating conditions) w l p h w l p h 9 7 [ ' 9 / , 1 9 7 + u h f 9 7 + g r p w l p h 9 5 [ ' 9 / , 1 g r p 9 / , 1 u h f w 7 ; s g i w 7 ; s g u w 5 ; s g i w 5 ; s g u $ * 9 table 35. operational amplifier symbol parameter test condition min. typ. max. unit gbw gbw product 1 3.5 7.0 mhz avol dc dc open loop gain 80 db psrr power supply rejection dc, v in = 150 mv 80 db v off input offset voltage -5 +5 mv v icr common mode input range -0.2 0 3 v v oh output voltage range high i load = 1 ma to gnd v s -0.2 v s v v ol output voltage range low i load = 1 ma to v s 0 0.2 v i lim+ output current limitation + dc 10 15 30 ma i lim- output current limitation - dc -10 -15 -30 ma sr+ slew rate positive 1 4 10 v/s sr- slew rate negative -1 -4 -10 v/s electrical specifications L99PM72PXP 70/128 doc id 023553 rev 3 5.5.14 spi the voltages are referred to ground and currents are assumed positive, when the current flows into the pin. 6v electrical specifications L99PM72PXP 72/128 doc id 023553 rev 3 the voltages are referred to ground and currents are assumed positive, when the current flows into the pin. 6 v < v s < 18 v; 4.8 v < v 1 < 5.2 v; all outputs open; t j = -40c to 130c, unless otherwise specified 5.5.15 inputs txdc and txdl for flash mode 6v ? v s ? 18 v; 4.5 v ? v 1 ? 5.3 v; t j = -40c to 130c; voltages are referred to pgnd, all outputs open figure 34. spi - transfer timing diagram the spi can be driven by a micro controller with its spi peripheral running in following mode: cpol = 0 and cpha = 0. for this mode input data is sampled by the low to high transition of the clock clk, and output data is changed from the high to low transition of clk. table 42. rxdl/nint, rxdc/nint timing symbol parameter test condition min. typ. max. unit t interupt interrupt pulse duration ? 56 ? s table 43. inputs: txdc and txdl for flash mode symbol parameter test cond ition min. typ. max. unit v flashl input low level (v txdc/l for exit from flash mode) v 1 = 5 v 7.1 8.4 9.0 v v flashh input high level (v txdc/l for transition into flash mode) v 1 = 5 v 8.3 9.4 10.0 v v flashhys input voltage hysteresis v 1 = 5 v 0.8 1.0 1.2 v & 6 1 & / . ' , ' 2 , q s x w ' d w d 5 h j l v w h u & 6 1 k l j k w r o r z ' 2 h q d e o h g w l p h ' , g d w d z l o o e h d f f h s w h g r q w k h u l v l q j h g j h r i & / . v l j q d o w l p h w l p h w l p h w l p h ' 2 g d w d z l o o f k d q j h r q w k h i d o o l q j h g j h r i & / . v l j q d o * o r e d o ( u u r u & 6 1 o r z w r k l j k d f w x d o g d w d l v w u d q v i h u h g w r r x w s x w s r z h u v z l w f k h v r o g g d w d q h z g d w d ; ; ; ; ; ; & r p p d q g % \ w h * o r e d o 6 w d w x v % \ w h ' d w d $ * 9 L99PM72PXP electrical specifications doc id 023553 rev 3 73/128 figure 35. spi input timing 9 & & 9 & & 9 & & 9 & & 9 & & 9 & & 9 d o l g 9 d o l g & 6 1 & / . ' , w v h w & 6 1 w & / . + w v h w & / . w & / . / w k r o g ' , w v h w ' , $ * 9 electrical specifications L99PM72PXP 74/128 doc id 023553 rev 3 figure 36. spi output timing (part 1) 7 i & / . 7 u & / . & / . 9 f f 9 f f 9 f f ' 2 o r z w r k l j k 9 f f 9 f f 7 u ' 2 7 g ' 2 9 f f 9 f f 7 i ' 2 ' 2 k l j k w r o r z 7 i & 6 1 7 u & 6 1 & 6 1 9 f f 9 f f 9 f f 7 h q ' 2 b w u l b / 7 h q ' 2 b w u l b + 7 g l v ' 2 b / b w u l 7 g l v ' 2 b + b w u l $ * 9 L99PM72PXP electrical specifications doc id 023553 rev 3 75/128 figure 37. spi csn - output timing figure 38. spi - csn low to high tr ansition and global status bit access & 6 1 g 2 1 w w u l q i l q w 2 ) ) w g 2 ) ) w 2 ) ) v w d w h 2 1 v w d w h 2 ) ) v w d w h 2 1 v w d w h 2 1 w r x w s x w f x u u h q w r i d g u l y h u r x w s x w f x u u h q w r i d g u l y h u & 6 1 o r z w r k l j k g d w d i u r p v k l i w u h j l v w h u l v w u d q v i h u u h g w r r x w s x w s r z h u v z l w f k h v w & 6 1 b + , p l q $ * 9 & 6 1 & / . ' , ' 2 & 6 1 k l j k w r o r z d q g & / . v w d \ v o r z v w d w x v l q i r u p d w l r q r i g d w d e l w i d x o w f r q g l w l r q l v w u d q v i h u h g w r ' 2 ' , g d w d l v q r w d f f h s w h g ' 2 v w d w x v l q i r u p d w l r q r i g d w d e l w i d x o w f r q g l w l r q z l o o v w d \ d v o r q j d v & 6 1 l v o r z w l p h w l p h w l p h w l p h $ * 9 st spi L99PM72PXP 76/128 doc id 023553 rev 3 6 st spi 6.1 spi communication flow 6.1.1 general description the spi communication is based on a standard spi interface structure using csn (chip select not), sdi (serial data in), sdo (serial data out/error) and sck (serial clock) signal lines. at device start-up the master reads the L99PM72PXP st spi doc id 023553 rev 3 77/128 6.1.2 operating code definition the st spi L99PM72PXP 78/128 doc id 023553 rev 3 figure 39. read configuration register 1. the configuration register is implemented for comp liance with st standard spi 3.0 and contains only the watchdog trigger bit at d0. figure 40. write configuration register 1. the configuration register is implemented for comp liance with st standard spi 3.0 and contains only the watchdog trigger bit at d0. & 6 1 6 ' , & r p p d q g ) d l o 6 d i h 9 v ) d l o 9 ) d l o 7 6 ' 7 6 ' 1 2 7 & k l s 5 h v 2 5 & r p p ( u u & r p ( u u r u * ( ) 6 ' 2 * o r e d o 6 w d w x v 7 5 , * $ * 9 & 6 1 6 ' , & r p p d q g ) d l o 6 d i h 9 v ) d l o 9 ) d l o 7 6 ' 7 6 ' 1 2 7 & k l s 5 h v 2 5 & r p p ( u u & r p ( u u r u * ( ) 6 ' 2 * o r e d o 6 w d w x v 7 5 , * q 7 5 , * q $ * 9 L99PM72PXP st spi doc id 023553 rev 3 79/128 6.1.5 address mapping the ram memory area consists of 16 bit registers. for the device information (rom memory area) the eight most significant bits of the memory cell are used. the remaining 8 are zero. all unused ram and rom addresses are read as ?0?. note: the register definition for ram address 00h is unused. a register value of all 0 must cause the device to enter a fail-safe state (interpreted as ?sdi stuck to gnd? failure). note: rom address 3fh is unused. an attempt to access this address must be recognized as a communication error (?sdi stuck to v cc ? failure) and must cause the device to enter a fail-safe state. 6.1.6 write operation the write operation starts with a command byte followed by 2, data bytes. the number of data bytes is specified in the st spi L99PM72PXP 80/128 doc id 023553 rev 3 oc0, oc1: operating code (00 for ?write? mode) a0 to a5: address bits an attempt to write 00h at ram address 00h is recognized as a failure (sdi stuck to gnd). the device enters a fail-safe state. 6.1.7 format of data shifted ou t at sdo during write cycle failures are indicated by activating the corresponding bit of the L99PM72PXP st spi doc id 023553 rev 3 81/128 figure 41. format of data shifted out at sdo during write cycle 6.1.8 read operation oc0, oc1: operating code (01 for ?read? mode) a0 to a5: address bits $ $ $ $ $ $ & 6 1 6 ' , & r p p d q g ' ' ' ' ' ' ' ' ) d l o 6 d i h 9 v ) d l o 9 ) d l o 7 6 ' 7 6 ' 1 2 7 & k l s 5 h v 2 5 & r p p ( u u & r p ( u u r u * ( ) 6 ' 2 * o r e d o 6 w d w x v v w ' d w d e \ w h s u h y l r x v f r q w h q w r i u h j l v w h u ' ' ' ' ' ' ' ' q g ' d w d e \ w h s u h y l r x v f r q w h q w r i u h j l v w h u ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' v w ' d w d e \ w h q g ' d w d e \ w h $ * 9 table 55. read command format: command byte msb lsb op code address 0 1 a5 a4 a3 a2 a1 a0 table 56. read command format: data byte 1 msb lsb 00000000 table 57. read command format: data byte 2 msb lsb 00000000 st spi L99PM72PXP 82/128 doc id 023553 rev 3 6.1.9 format of data shifted ou t at sdo duri ng read cycle failures are indicated by activating the corresponding bit of the L99PM72PXP st spi doc id 023553 rev 3 83/128 6.1.10 read and cl ear status operation the ?read and clear status? operation starts with a command byte followed 2 data bytes. the number of data bytes is specified in the st spi L99PM72PXP 84/128 doc id 023553 rev 3 failures are indicated by activating the corresponding bit of the L99PM72PXP st spi doc id 023553 rev 3 85/128 the st spi L99PM72PXP 86/128 doc id 023553 rev 3 br: burst-mode read (1 = burst-mode read is supported) wd: watchdog (1 = available, 0 = not available) 32-, 24-, 16-bit: width of spi frame L99PM72PXP st spi doc id 023553 rev 3 87/128 6.2.2 o verview control register 001001 ctrl register9 001010 ctrl register10 001011 ctrl register11 001100 ctrl register12 001101 ctrl register13 001110 ctrl register14 001111 ctrl register15 010000 ctrl register16 100010 ctrl register34 100011 ctrl register35 111111 configuration register table 75. spi register: stat register selection stat register. 1?3 stat register selection 010001 stat register1 010010 stat register2 010011 stat register3 010100 stat register4 010101 stat register5 table 74. spi register: ctrl register selection (continued) ctrl register 1?6 ctrl register selection table 76. overview of control register data bytes 1 st data byte <15:8> 2 nd data byte <7:0> control register 1, data default0000000000000000 function ouths ouths out4 out4 ouths_ext out3 out2 out1 rel2 rel1 v2 v2 parity stby sel go stby tr i g group hs control ls output, v2 and mode control st spi L99PM72PXP 88/128 doc id 023553 rev 3 control register 2, data default0000000000000111 function reserved wu3_filt wu3_filt wu2_filt wu2_filt wu1_filt wu1_filt reserved wu3_pu/pd wu2_pu/pd wu1_pu/pd reserved wu3_en wu2_en wu1_en group wake-up control wake-up control control register 3, data default0000000000001100 function reserved t1_on t1_per_msb t1_per_lsb reserved t2_on t2_per_msb t2_per_lsb reserved wd_time_msb wd_time_lsb lin wu en can wu en wake timer en wake time sel group timer settings watchdog and cyclic wake up settings control register 4, data default0001010011100000 function reserved icmp ouths_rec_en vlock_out_en reserved ls ov/uv shutdown_en v1reset_level v1reset_level lin pu en reserved lin txd tout en can_act can_loop_en reserved can_rec_only group control (other) transceiver settings control register 5, data default0111111100000000 function reserved pwm2_off_dc_6 pwm2_off_dc_5 pwm2_off_dc_4 pwm2_off_dc_3 pwm2_off_dc_2 pwm2_off_dc_1 pwm2_off_dc_0 pwm freq pwm1_on_dc_6 pwm1_on_dc_5 pwm1_on_dc_4 pwm1_on_dc_3 pwm1_on_dc_2 pwm1_on_dc_1 pwm1_on_dc_0 group pwm2 setting pwm1 setting table 76. overview of control register data bytes (continued) 1 st data byte <15:8> 2 nd data byte <7:0> L99PM72PXP st spi doc id 023553 rev 3 89/128 control register 6, data default0111111100000000 function reserved pwm4_off_dc_6 pwm4_off_dc_5 pwm4_off_dc_4 pwm4_off_dc_3 pwm4_off_dc_2 pwm4_off_dc_1 pwm4_off_dc_0 reserved pwm3_on_dc_6 pwm3_on_dc_5 pwm3_on_dc_4 pwm3_on_dc_3 pwm3_on_dc_2 pwm3_on_dc_1 pwm3_on_dc_0 group pwm4 setting pwm3 setting control register 7, data default0000000000000000 function ext_id_15 ext_id_14 ext_id_13 ext_id_12 ext_id_11 ext_id_10 ext_id_9 ext_id_8 ext_id_7 ext_id_6 ext_id_5 ext_id_4 ext_id_3 ext_id_2 ext_id_1 ext_id_0 group selective wakeup settings control register 8, data default0000000000000000 function reserved id_10 id_9 id_8 id_7 id_6 id_5 id_4 id_3 id_2 id_1 id_0 ext_id_17 ext_id_16 group selective wakeup settings control register 9, data default0000000000000000 function reserved can_ide dlc_3 dlc_2 dlc_1 dlc_0 group selective wakeup settings control register 10, data default0000000000000000 function data byte 2 data byte 1 group selective wakeup settings table 76. overview of control register data bytes (continued) 1 st data byte <15:8> 2 nd data byte <7:0> st spi L99PM72PXP 90/128 doc id 023553 rev 3 control register 11, data default0000000000000000 function data byte 4 data byte 3 group selective wakeup settings control register 12, data default0000000000000000 function data byte 6 data byte 5 group selective wakeup settings control register 13, data default0000000000000000 function data byte 8 data byte 7 group selective wakeup settings control register 14, data default0000000000000000 function ext_id_ mask_15 ext_id_ mask_14 ext_id_ mask_13 ext_id_ mask_12 ext_id_ mask_11 ext_id_ mask_10 ext_id_ mask_9 ext_id_ mask_8 ext_id_ mask_7 ext_id_ mask_6 ext_id_ mask_5 ext_id_ mask_4 ext_id_ mask_3 ext_id_ mask_2 ext_id_ mask_1 ext_id_ mask_0 group selective wakeup settings control register 15, data defaults0000000000000000 function reserved id_mask_10 id_mask_9 id_mask_8 id_mask_7 id_mask_6 id_mask_5 id_mask_4 id_mask_3 id_mask_2 id_mask_1 id_mask_0 ext_id_ mask_17 ext_id_ mask_16 group selective wakeup settings control register 16, data defaults0000000001010000 function cr16_30 cr16_21 cr16_20 cr16_14 cr16_13 cr16_12 cr16_11 cr16_10 reserved samp 2 samp 1 samp 0 reserved br1 br2 sw_en group selective wakeup settings table 76. overview of control register data bytes (continued) 1 st data byte <15:8> 2 nd data byte <7:0> L99PM72PXP st spi doc id 023553 rev 3 91/128 note: reserved bit must be kept at their default values. writing to other register address is not allowed 6.2.3 control register 1 control register 34, data defaults0000000000000001 function reserved wd_en control register 35, data defaults0000000000110110 function reserved cr35_25 cr35_24 cr35_23 cr35_22 cr35_21 cr35_20 cr35_10 configuration register, data defaults0000000000000000 function reserved trig table 76. overview of control register data bytes (continued) 1 st data byte <15:8> 2 nd data byte <7:0> table 77. control register 1: command and data bytes command byte 1 st data byte 2 nd data byte read/write address x x 0 0 0 0 0 1 data, 8bit data, 8 bit table 78. control register 1, data bytes 1 st data byte <15:8> 2 nd data byte <7:0> defaults0000000000000000 function ouths_2 ouths_1 out4_2 out4_1 ouths_ext out3 out2 out1 rel2 rel1 v2_2 v2_1 parity stby_sel go_stby tr i g group hs control ls output, v2 and mode control st spi L99PM72PXP 92/128 doc id 023553 rev 3 table 79. control register 1, bits bit name comment 15 ouths select mode of ouths 14 ouths_ext ouths_2 ouths_1 mode 000hs off active and standby mode 001 hs cyclic on with timer 1 0 1 0 hs controlled by pwm4 011 hs cyclic on with timer 2 110pwm3 1x1hs on 13 out4 select mode of out4 12 out4_2 out4_1 mode 00hs off active and standby mode 01hs on 10 hs controlled by pwm4 11 hs cyclic on with timer 2 11 ouths_ext extended function of ouths; see ouths 10 out3 select mode of out3 out3 mode 0 select fso active and standby mode 1 select pwm3 L99PM72PXP st spi doc id 023553 rev 3 93/128 9 out2 select mode of out2 out2 mode 0 select pwm2 active and standby mode 1 select timer2 8 out1 select mode of out1 out1 mode 0 select pwm1 active and standby mode 1 select timer1 7 rel2 select mode of rel2 rel2 mode 0 rel2 off active and standby mode 1 rel2 on active mode 6 rel1 select mode of rel1 rel1 mode 0 rel1 off active and standby mode 1 rel1 on active mode table 79. control register 1, bits (continued) bit name comment st spi L99PM72PXP 94/128 doc id 023553 rev 3 5v 2 4 v 2_2 v 2_1 00v 2 off in all modes 01 v 2 on in active mode; off in v 1 /v bat_standby mode 10 v 2 on in active/v 1 _ standby mode; off in v bat_standby mode 11v 2 on in all modes 3 parity the stby_sel and go_stby bits are protected by a parity check the bits stby_sel, go_stby and parity mu st represent an even number of '1', otherwise the command is ignored and the communication error bit is set in the global status register. following are the valid settings parity stby_se l go_stby command 0 1 1 go to v 1 _ standby 1 0 1 go to v bat_standby 0 0 0 no transition to standby 1 1 0 no transition to standby 2 stby_sel select standby mode 0v bat_standby mode 1v 1_standby mode 1 go_stby execute standby mode 0 no action 1 execute standby mode 0 trig trigger bit for watchdog table 79. control register 1, bits (continued) bit name comment L99PM72PXP st spi doc id 023553 rev 3 95/128 6.2.4 control register 2 table 80. control register 2: command and data bytes command byte 1 st data byte 2 nd data byte read/write address x x 0 0 0 0 1 0 data, 8bit data, 8 bit table 81. control register 2, data bytes 1 st data byte <15:8> 2 nd data byte <7:0> defaults 000000000000 111 function reserved wu3_filt_msb wu3_filt_lsb wu2_filt_msb wu2_filt_lsb wu1_filt_msb wu1_filt_lsb reserved wu3_pu/pd wu2_pu/pd wu1_pu/pd reserved wu3_en wu2_en wu1_en group wakeup control wakeup control table 82. control register 2, bits bit name comment 15 reserved must be kept at default 14 reserved must be kept at default 13, 12 wu3_filt wakeup filter configuration 11, 10 wu2_filt msb lsb 9, 8 wu1_filt 0 0 static, 64 s 0 1 enabled with timer 2; 80 s blank 1 0 enabled with timer 2; 800 s blank 1 1 enabled with timer 1; 800 s blank 7 reserved must be kept at default 6 wu3_pu/pd pull up or pull down configuration 5 wu2_pu/pd 0 pull down 4 wu1_pu/pd 1 pull up 3 reserved must be kept at default 2 wu3_en enable wake up source 1 wu2_en 0 disable 0 wu1_en 1 enable st spi L99PM72PXP 96/128 doc id 023553 rev 3 6.2.5 control register 3 table 83. control register 3: command and data bytes command byte 1 st data byte 2 nd data byte read/write address x x 0 0 0 0 1 1 data, 8bit data, 8 bit table 84. control register 3, data bytes 1 st data byte <15:8> 2 nd data byte <7:0> defaults0000000000001100 function reserved t1_on t1_per_msb t1_per_lsb reserved t2_on t2_per_msb t2_per_lsb reserved wd_time_msb wd_time_lsb lin_wu_en can_wu_en wake_timer_en wake_timer_select group timer settings watchdog and cyclic wake up settings table 85. control register 3, bits bit name comment 15 reserved must be kept at default 14 t1_on timer 1 ?on? time selections 010ms 120ms 13 t1_per_msb timer 1 period selection 12 t1_per_lsb msb lsb 00 1s 01 2s 10 3s 11 4s timer 1 is restarted with a valid write command to control register 3 11 reserved must be kept at default 10 t2_on timer 2 ?on? time selection 00.1ms 11ms L99PM72PXP st spi doc id 023553 rev 3 97/128 9 t2_per_msb timer 2 period selection 8 t2_per_lsb msb lsb 0010ms 0120ms 1050ms 1 1 200 ms timer 2 is restarted with a valid write command to control register 3 7 reserved must be kept at default 6 reserved must be kept at default 5 wd_time_msb trigger window selection 4 wd_time_lsb msb lsb 0010ms 0150ms 1 0 100 ms 1 1 200 ms 3 lin_wu_en enable lin as wake up source 0disabled 1 enabled 2 can_wu_en enable can as wake up source 0disabled 1 enabled 1 wake_timer_en enable wake up by timer from v 1_standby mode (interrupt) or v bat_standby mode (n reset ) 0disabled 1 enabled 0 wake_timer_select timer selection for timer interrupt / wake-up of c by timer 0timer 2 1timer 1 table 85. control register 3, bits (continued) bit name comment st spi L99PM72PXP 98/128 doc id 023553 rev 3 6.2.6 control register 4 table 86. control register 4: command and data bytes command byte 1 st data byte 2 nd data byte read/write address x x 0 0 0 1 0 0 data, 8bit data, 8 bit table 87. control register 4, data bytes 1 st data byte <15:8> 2 nd data byte <7:0> defaults0001010011100000 function reserved icmp ouths_rec_en vlock_out_en reserved ls_ov/uv_shutdown_en v1reset_level_2 v1reset_level_1 lin_pu_en reserved lin_txd_tout_en can_act can_loop_en reserved can_rec_only group control (other) transceiver settings table 88. control register 4, bits bit name comment 15 reserved must be kept at default 14 icmp v 1 load current supervision 0 enabled; watchdog is disabled in v 1 standby when the v 1loadcurrent < i cmpthreshold 1 disabled; watchdog is automatically disabled when v 1 standby is entered 13 ouths_rec_en overcurrent auto recovery mode for ouths 0 disabled 1 enabled 12 vlock_out_en voltage lock out: ov/uv status 0 overvoltage/undervoltage status recovers automatically when condition disappears 1 overvoltage/undervoltage status is latched until a read and clear command is performed 11 reserved must be kept at default L99PM72PXP st spi doc id 023553 rev 3 99/128 10 ls_ov/uv shutdown_en shutdown of low-side drivers in case of overvoltage/undervoltage 0 no shutdown of low-sides in case of overvoltage/undervoltage 1 shutdown low-sides in case of overvoltage/undervoltage 9 v1reset_level_1 select reset level 8 v1reset_level_2 v1reset_level_ 2 v1reset_level_1 v1 reset level 004.6v 0 1 4.35 v 104.1v 113.8v 7 lin_pu_en enable internal lin pull up 0 no lin master pull-up 1 lin master pull-up 6 reserved must be kept at default 5 lin_txd_tout_en enable / disable monitoring via txd 0 no txd monitoring 1 txd monitoring; lin transmitter is switched off if txdl is dominant for t > 12 ms 4 can_act activate can transceiver controls the can transceiver mode transition between 'can trx standby' mode and 'trx normal' mode. the bit can_act is automatically rese t to '0' when the device enters v 1_standby mode or v bat_standby mode. 0 can trx standby mode 1 trx normal mode see section 2.9.1 for details. table 88. control register 4, bits (continued) bit name comment st spi L99PM72PXP 100/128 doc id 023553 rev 3 6.2.7 control register 5 3 can_loop_en enable looping of cantx to canrxd 0 no looping 1 txdc is looped to rxdc 2 reserved must be kept at default 1 reserved must be kept at default 0 can_rec_only enable can receive only mode 0 can in transceiver mode active mode 1 can in receive only mode table 88. control register 4, bits (continued) bit name comment table 89. control register 5: command and data bytes command byte 1 st data byte 2 nd data byte read/write address x x 0 0 0 1 0 1 data, 8bit data, 8 bit table 90. control register 5, data bytes 1 st data byte <15:8> 2 nd data byte <7:0> defaults0111111100000000 function reserved pwm2_off_dc_6 pwm2_off_dc_5 pwm2_off_dc_4 pwm2_off_dc_3 pwm2_off_dc_2 pwm2_off_dc_1 pwm2_off_dc_0 pwm_freq pwm1_on_dc_6 pwm1_on_dc_5 pwm1_on_dc_4 pwm1_on_dc_3 pwm1_on_dc_2 pwm1_on_dc_1 pwm1_on_dc_0 group pwm2 setting pwm1 setting L99PM72PXP st spi doc id 023553 rev 3 101/128 table 91. control register 5, bits bit name comment 15 reserved must be kept at default 14 pwm2_ off_dc_6 pwm2 duty cycle 13 pwm2_ off_dc_5 pwm2 off_ dc_6 pwm2 off_ dc_5 pwm2 off_ dc_4 pwm2 off_ dc_3 pwm2 off_ dc_2 pwm2 off_ dc_1 pwm2 off_ dc_0 pwm2 duty cycle 12 pwm2_ off_dc_4 11111110%, hs off 11 pwm2_ off_dc_3 ... 10 pwm2_ off_dc_2 000001098.5% 9 pwm2_ off_dc_1 000000199.25% 8 pwm2_ off_dc_0 0000000100% hs on 7 pwm_freq select pwm frequency 0128hz 1256hz 6 pwm1_ on_dc_6 pwm1 duty cycle 5 pwm1_ on_dc_5 pwm1 on_ dc_6 pwm1 on_ dc_5 pwm1 on_ dc_4 pwm1 on_ dc_3 pwm1 on_ dc_2 pwm1 on_ dc_1 pwm1 on_ dc_0 pwm1 duty cycle 4 pwm1_ on_dc_4 1111111100%, hs on 3 pwm1_ on_dc_3 ... 2 pwm1_ on_dc_2 00000101.5% 1 pwm1_ on_dc_1 00000010.75% 0 pwm1_ on_dc_0 00000000% hs off st spi L99PM72PXP 102/128 doc id 023553 rev 3 6.2.8 control register 6 table 92. control register 6: command and data bytes command byte 1 st data byte 2 nd data byte read/write address x x 0 0 0 1 1 0 data, 8bit data, 8 bit table 93. control register 6, data bytes 1 st data byte <15:8> 2 nd data byte <7:0> defaults0111111100000000 function reserved pwm4_off_dc_6 pwm4_off_dc_5 pwm4_off_dc_4 pwm4_off_dc_3 pwm4_off_dc_2 pwm4_off_dc_1 pwm4_off_dc_0 reserved pwm3_on_dc_6 pwm3_on_dc_5 pwm3_on_dc_4 pwm3_on_dc_3 pwm3_on_dc_2 pwm3_on_dc_1 pwm3_on_dc_0 group pwm4 setting pwm3 setting table 94. control register 6, bits bit name comment 15 reserved must be kept at default 14 pwm4_ off_dc_6 pwm4 duty cycle 13 pwm4_ off_dc_5 pwm4 off_ dc_6 pwm4 off_ dc_5 pwm4 off_ dc_4 pwm4 off_ dc_3 pwm4 off_ dc_2 pwm4 off_ dc_1 pwm4 off_ dc_0 pwm4 duty cycle 12 pwm4_ off_dc_4 11111110%, hs off 11 pwm4_ off_dc_3 ... 10 pwm4_ off_dc_2 000001098.5% 9 pwm4_ off_dc_1 000000199.25% 8 pwm4_ off_dc_0 0000000100% hs on 7 reserved must be kept at default L99PM72PXP st spi doc id 023553 rev 3 103/128 6 pwm3_ on_dc_6 pwm3 duty cycle 5 pwm3_ on_dc_5 pwm3 on_ dc_6 pwm3 on_ dc_5 pwm3 on_ dc_4 pwm3 on_ dc_3 pwm3 on_ dc_2 pwm3 on_ dc_1 pwm3 on_ dc_0 pwm3 duty cycle 4 pwm3_ on_dc_4 1111111100%, hs on 3 pwm3_ on_dc_3 ... 2 pwm3_ on_dc_2 00000101.5% 1 pwm3_ on_dc_1 00000010.75% 0 pwm3_ on_dc_0 00000000% hs off table 94. control register 6, bits (continued) bit name comment st spi L99PM72PXP 104/128 doc id 023553 rev 3 6.2.9 control register 7 table 95. control register 7: command and data bytes command byte 1 st data byte 2 nd data byte read/write address x x 0 0 0 1 1 1 data, 8bit data, 8 bit table 96. control register 7, data bytes 1 st data byte <15:8> 2 nd data byte <7:0> defaults0000000000000000 function ext_id_15 ext_id_14 ext_id_13 ext_id_12 ext_id_11 ext_id_10 ext_id_9 ext_id_8 ext_id_7 ext_id_6 ext_id_5 ext_id_4 ext_id_3 ext_id_2 ext_id_1 ext_id_0 group selective wakeup settings table 97. control register 7, bits bit name comment 15 ext_id_15 extended can identifier definition of which extended can identifier will wake up to run matching on extended can identifier also can ide (control register 9 must be set) 14 ext_id_14 13 ext_id_13 12 ext_id_12 11 ext_id_11 10 ext_id_10 9 ext_id_9 8 ext_id_8 7 ext_id_7 6 ext_id_6 5 ext_id_5 4 ext_id_4 3 ext_id_3 2 ext_id_2 1 ext_id_1 0 ext_id_0 L99PM72PXP st spi doc id 023553 rev 3 105/128 6.2.10 control register 8 table 98. control register 8: command and data bytes command byte 1 st data byte 2 nd data byte read/write address x x 0 0 1 0 0 0 data, 8 bit data, 8 bit table 99. control register 8, data bytes 1 st data byte <15:8> 2 nd data byte <7:0> defaults0000 000000000000 function reserved id_10 id_9 id_8 id_7 id_6 id_5 id_4 id_3 id_2 id_1 id_0 ext_id_17 ext_id_16 group selective wakeup settings table 100. control register 8, bits bit name comment 15 reserved must be kept at default 14 reserved 13 reserved 12 id_10 standard can identifier definition of which standard can identifier will wake up 11 id_9 10 id_8 9id_7 8id_6 7id_5 6id_4 5id_3 4id_2 3id_1 2id_0 1 ext_id_17 extend ed can identifier definition of which extended can identifier will wake up to run matching on extended can identifier also can ide (control register 9 must be set) 0ext_id_16 st spi L99PM72PXP 106/128 doc id 023553 rev 3 6.2.11 control register 9 table 101. control register 9: command and data bytes command byte 1 st data byte 2 nd data byte read/write address x x 0 0 1 0 0 1 data, 8 bit data, 8 bit table 102. control register 9, data bytes 1 st data byte <15:8> 2 nd data byte <7:0> defaults0000 000000000000 function reserved can_ide dlc_3 dlc_2 dlc_1 dlc_0 group selective wakeup settings table 103. control register 9, bits bit name comment 15 reserved must be kept at default 14 reserved 13 reserved 12 reserved 11 reserved 10 reserved 9 reserved 8 reserved 7 reserved 6 reserved 5 reserved 4 can_ide can ide bit 1 can identifier matching based on can extended message format 0 can identifier matching based on can standard message format 3 dlc_3 data length code defines the amount of data bytes used for the data matching. possible values up to 8 byte according to can message format 2 dlc_2 1 dlc_1 0 dlc_0 L99PM72PXP st spi doc id 023553 rev 3 107/128 6.2.12 control register 10 6.2.13 control register 11 table 104. control register 10: command and data bytes command byte 1 st data byte 2 nd data byte read/write address x x 0 0 1 0 1 0 data, 8 bit data, 8 bit table 105. control register 10, data bytes 1 st data byte <15:8> 2 nd data byte <7:0> defaults0000 000000000000 function data byte2 data byte1 group selective wakeup settings table 106. control register 10, bits bit name comment 15 - 8 data byte2 data field for data matching 7 - 0 data byte1 data field for data matching table 107. control register 11: command and data bytes command byte 1 st data byte 2 nd data byte read/write address x x 0 0 1 0 1 1 data, 8 bit data, 8 bit table 108. control register 11, data bytes 1 st data byte <15:8> 2 nd data byte <7:0> defaults0000 000000000000 function data byte4 data byte3 group selective wakeup settings table 109. control register 11, bits bit name comment 15 - 8 data byte4 data field for data matching 7 - 0 data byte3 data field for data matching st spi L99PM72PXP 108/128 doc id 023553 rev 3 6.2.14 control register 12 6.2.15 control register 13 table 110. control register 12: command and data bytes command byte 1 st data byte 2 nd data byte read/write address x x 0 0 1 1 0 0 data, 8 bit data, 8 bit table 111. control register 12, data bytes 1 st data byte <15:8> 2 nd data byte <7:0> defaults0000 000000000000 function data byte6 data byte5 group selective wakeup settings table 112. control register 12, bits bit name comment 15 - 8 data byte6 data field for data matching 7 - 0 data byte5 data field for data matching table 113. control register 13: command and data bytes command byte 1 st data byte 2 nd data byte read/write address x x 0 0 1 1 0 1 data, 8 bit data, 8 bit table 114. control register 13, data bytes 1 st data byte <15:8> 2 nd data byte <7:0> defaults0000 000000000000 function data byte8 data byte7 group selective wakeup settings table 115. control register 13, bits bit name comment 15 - 8 data byte8 data field for data matching 7 - 0 data byte7 data field for data matching L99PM72PXP st spi doc id 023553 rev 3 109/128 6.2.16 control register 14 table 116. control register 14: command and data bytes command byte 1 st data byte 2 nd data byte read/write address x x 0 0 1 1 1 0 data, 8 bit data, 8 bit table 117. control register 14, data bytes 1 st data byte <15:8> 2 nd data byte <7:0> defaults0000 000000000000 function ext_id_msk_15 ext_id_msk_14 ext_id_msk_13 ext_id_msk_12 ext_id_msk_11 ext_id_msk_10 ext_id_msk_9 ext_id_msk_8 ext_id_msk_7 ext_id_msk_6 ext_id_msk_5 ext_id_msk_4 ext_id_msk_3 ext_id_msk_2 ext_id_msk_1 ext_id_msk_0 group selective wakeup settings table 118. control register 14, bits bit name comment 15 ext_id_msk_15 masking bits for extended can identifier 14 ext_id_msk_14 1 extended can identifier bit is ignored for matching 13 ext_id_msk_13 0 extended can identifier bit is matched 12 ext_id_msk_12 to run matching on extended can id entifier also can_ide (control register 9 must be set) 11 ext_id_msk_11 10 ext_id_msk_10 9 ext_id_msk_9 8 ext_id_msk_8 7 ext_id_msk_7 6 ext_id_msk_6 5 ext_id_msk_5 4 ext_id_msk_4 3 ext_id_msk_3 2 ext_id_msk_2 1 ext_id_msk_1 0 ext_id_msk_0 st spi L99PM72PXP 110/128 doc id 023553 rev 3 6.2.17 control register 15 table 119. control register 15: command and data bytes command byte 1 st data byte 2 nd data byte read/write address x x 0 0 1 1 1 1 data, 8bit data, 8 bit table 120. control register 15, data bytes 1 st data byte <15:8> 2 nd data byte <7:0> defaults0000 000000000000 function reserved id_msk_10 id_msk_9 id_msk_8 id_msk_7 id_msk_6 id_msk_5 id_msk_4 id_msk_3 id_msk_2 id_msk_1 id_msk_0 ext_id_msk_17 ext_id_msk_16 group selective wakeup settings table 121. control register 15, bits bit name comment 15 reserved must be kept at default 14 reserved 13 reserved 12 id_msk_10 masking bits for standard can identifier 11 id_msk_9 1 standard can identifier bit is ignored for matching 10 id_msk_8 0 standard can identifier bit is matched 9 id_msk_7 8 id_msk_6 7 id_msk_5 6 id_msk_4 5 id_msk_3 4 id_msk_2 3 id_msk_1 2 id_msk_0 1 ext_id_msk_17 masking bits for extended can identifier 0 ext_id_msk_16 1 extended can identifier bit is ignored for matching 0 extended can identifier bit is matched to run matching on extended can id entifier also can_ide (control register 9 must be set) L99PM72PXP st spi doc id 023553 rev 3 111/128 6.2.18 control register 16 table 122. control register 16: command and data bytes command byte 1 st data byte 2 nd data byte read/write address x x 0 1 0 0 0 0 data, 8 bit data, 8 bit table 123. control register 16, data bytes 1 st data byte <15:8> 2 nd data byte <7:0> defaults0000 000000000000 function cr16_30 cr16_21 cr16_20 cr16_14 cr16_13 cr16_12 cr16_11 cr16_10 reserved sample_2 sample_1 sample_0 reserved br_1 br_0 sw_en group selective wakeup settings table 124. control register 16, bits bit name comment 15 cr16_30 (1) must be kept at default 14 cr16_21 13 cr16_20 12 cr16_14 11 cr16_13 10 cr16_12 9 cr16_11 8 cr16_10 7 reserved must be kept at default 6 sample_2 sample point 5 sample_1 sample_2 sample_1 sample_0 sample point 4 sample_0 0 0 0 71.5 % 0 0 1 73.5 % 0 1 0 75.5 % 0 1 1 77.5 % 1 0 0 79.5 % 1 0 1 81.5 % (optimum sample point (2) ) 1 1 0 83.5 % 1 1 1 85.5 % st spi L99PM72PXP 112/128 doc id 023553 rev 3 3 reserved must be kept at default 2 br_1 can baud rate 1br_0 br_1 br_0 baud rate 0 0 500 kbaud 0 1 250 kbaud 1 1 125 kbaud 0 sw_en selective wakeup enable 0 no selective wakeup 1 selective wakeup enabled see section 2.9.2 1. changing the default configuration of cr16 (bits 1 to 15) is only possible when sele ctive wake is disabled (sw_en = 0). setting sw_en = 0 is always possible. setting sw_en = 1 must follow the procedure as described in section 2.9.2 . 2. the sampling point bits [6:4] have to be programmed to ?101? (81.5%) before enabling the selective wake- up feature. table 124. control register 16, bits (continued) bit name comment L99PM72PXP st spi doc id 023553 rev 3 113/128 6.2.19 control register 34 table 125. control register 34: command and data bytes command byte 1 st data byte 2 nd data byte read/write address x x 1 0 0 0 1 0 data, 8 bit data, 8 bit table 126. control register 34, data bytes 1 st data byte <15:8> 2 nd data byte <7:0> defaults0000 000000000001 function reserved wd_en group selective wakeup settings table 127. control register 34, bits bit name comment 15 reserved must be kept at default 14 reserved 13 reserved 12 reserved 11 reserved 10 reserved 9reserved 8reserved 7reserved 6reserved 5reserved 4reserved 3reserved 2reserved 1reserved 0 wd_en watchdog enabled bit 0 watchdog disabled 1 watchdog enabled writing to this bit is only possible during can flash mode (v txdl >v flash ). see section 2.2.2: flash mode . st spi L99PM72PXP 114/128 doc id 023553 rev 3 6.2.20 control register 35 table 128. control register 35: command and data bytes command byte 1 st data byte 2 nd data byte read/write address x x 1 0 0 0 1 1 data, 8 bit data, 8 bit table 129. control register 35, data bytes 1 st data byte <15:8> 2 nd data byte <7:0> defaults0000 000000110110 function reserved cr35_25 cr35_24 cr35_23 cr35_22 cr35_21 cr35_20 cr35_10 group selective wakeup settings table 130. control register 35, bits bit name comment 15 reserved must be kept at default 14 reserved 13 reserved 12 reserved 11 reserved 10 reserved 9reserved 8reserved 7reserved 6 cr35_25 must be kept at default 5 cr35_24 4 cr35_23 3 cr35_22 2 cr35_21 1 cr35_20 0 cr35_10 must be kept at default L99PM72PXP st spi doc id 023553 rev 3 115/128 6.2.21 overview status register table 131. overview of status register data bytes 1 st data byte <15:8> 2 nd data byte <7:0> status register 1, data <15:0> function ol_hs ol_out4 ol_out3 ol_out2 ol_out1 uv v2_fail v2_short ov oc_hs oc_out4 oc_out3 oc_out2 oc_out1 oc_rel2 oc_rel1 group diagnosis 1 diagnosis 2 status register 2, data <15:0> function wu3_state wu2_state wu1_state wu3_wake wu2_wake wu1_wake wake_can wake_lin wake_timer_int lin_perm_dom lin_txd_perm_dom lin_perm_rec can_rxd_ perm_rec can_perm_rec can_perm_dom can_txd_ perm_dom group diagnosis 3 diagnosis 4 status register 3, data <15:0> function tsd1 tw device_state device_state v1_fail v1_restart v1_restart v1_restart wd_fail wd_fail wd_fail wd_fail forced_sleep_wd forced_sleep_ tsd2_shtv1 wd_timer_state wd_timer_state group diagnosis 5 diagnosis 6 status register 4, data <15:0> function swrd_15 swrd_14 swrd_13 swrd_12 swrd_11 swrd_10 swrd_9 swr_d 8 swrd_7 sys_err tx_sync can_to wup wuf can_silent fd_err group diagnosis 7 diagnosis 8 status register 5, data <15:0> function reserved fecnt_4 fecnt_3 fecnt_2 fecnt_1 fecnt_0 osc_fail reserved osc_mon group diagnosis 9 diagnosis 10 st spi L99PM72PXP 116/128 doc id 023553 rev 3 6.2.22 global status register the global error flag is set once the watchdog failure counter (sr3<7:4>) is unequal to 0 (see also section 2.5: fail safe mode ). table 132. global status register bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 hex value global error flag (1) communication error (2) not (chip reset or comm error) (3) tsd2 (4) tsd1 v1 fail v s fail (ov/uv) (5) fail safe (6) active high/low high high low high high high high high default value in normal mode - after correct wd trigger or after read & clear on error flags 0010000020 power on 1000000080 power on weak battery (7) 1000001082 communication error 1 1 0 0 0 0 0 0 c0 v s overvoltage or undervoltage 1 0 1 0 0 0 1 0 a2 wd failure 10100001a1 spi error (di stuck) 10100001a1 tsd1 10101000a8 tsd2 10111001b9 v1 fail 10100100a4 other device failure (8) 10100000a0 1. the following status bits are reported in the global error flag: global status register: bits 6-0 status register 1: bits 10-0 status register 3: bits 15, 11, 7-2 2. communication error: invalid number of clock cycles during csn low or failed parity check on standby command. 3. cleared with clr command on sr3. 4. cleared with ?read and clear? on sr3 (-> tsd1) 5. diagnosis bit only, v s fail is not a fail-safe event; cleared by r ead&clear. bit is automatically cleared at (v s >v suv ) and (v s < v sov ) if vlock_out_en = 0 6. cleared with a valid wd trigger (wd fail) or by clearing the corresponding status register related to failure 7. slow v s ramp-up (v s undervoltage is filtered with 64s after power-on reset) 8. the global error flag is raised due to a failure condition which is not reported in the global status register. the failure i s reported in the status registers 1-5 L99PM72PXP st spi doc id 023553 rev 3 117/128 6.2.23 status register 1 table 133. status register 1: command and data bytes command byte 1 st data byte 2 nd data byte read/write address bit <15:8> bit <7:0> x x 0 1 0 0 0 1 data, 8bit data, 8 bit table 134. control register 1, data bytes 1 st data byte <15:8> 2 nd data byte <7:0> function ol_hs ol_out4 ol_out3 ol_out2 ol_out1 uv v2_fail v2_short ov oc_hs oc_out4 oc_out3 oc_out2 oc_out1 oc_rel2 oc_rel1 group diagnosis 1 diagnosis 2 table 135. status register 1, bits bit name comment information storage 15 ol_hs open-load event occurred since last read out bit is latched until a ?read and clear? access 14 ol_out4 13 ol_out3 12 ol_out2 11 ol_out1 10 uv under voltage event on v s occurred since last read out vlockouten (cr4) information storage 0 automatically reset when uv condition disappears 1 bit is latched until a ?read and clear? access 9v2_fail v 2 fail (v 2 < 2v for t> 2s) event occurred since last readout bit is latched until a ?read and clear? access 8 v2_short v 2 short (v 2 < 2 v for t > 4ms during start up) event occurred since last readout bit is latched until a ?read and clear? access st spi L99PM72PXP 118/128 doc id 023553 rev 3 7ov over voltage event on v s occurred since last read out vlockouten (cr4) information storage 0 automatically reset when ov condition disappears 1 bit is latched until a ?read and clear? access 6 oc_hs over current event occurred since last read out bit is latched until a ?read and clear? access 5oc_out4 4oc_out3 3oc_out2 2oc_out1 1oc_rel2 0oc_rel1 table 135. status register 1, bits (continued) bit name comment information storage L99PM72PXP st spi doc id 023553 rev 3 119/128 6.2.24 status register 2 table 136. status register 2: command and data bytes command byte 1 st data byte 2 nd data byte read/write address bit <15:8> bit <7:0> x x 0 1 0 0 1 0 data, 8bit data, 8 bit table 137. control register 2, data bytes 1 st data byte <15:8> 2 nd data byte <7:0> function wu3_state wu2_state wu1_state wu3_wake wu2_wake wu1_wake wake_can wake_lin wake_timer_int lin_perm_dom lin_txd_perm_dom lin_perm_rec can_rxd_perm_rec can_perm_rec can_perm_dom can_txd_perm_dom group diagnosis 3 diagnosis 4 table 138. status register 2, bits bit name comment information storage 15 wu3_state state of wux input; ?live bits? not clearable 14 wu2_state 13 wu1_state 12 wu3_wake shows wake up source (?1? = wake-up) bits are latched until a ?read and clear? access 11 wu2_wake 10 wu1_wake 9 wake_can 8 wake_lin 7 wake_timer_int st spi L99PM72PXP 120/128 doc id 023553 rev 3 6.2.25 status register 3 6 lin_perm_dom lin bus is dominant for t > 12 ms bits are latched until a ?read and clear? access 5 lin_txd_perm_dom txdl pin is dominant for t > 12 ms; transmitter is disabled 4 lin_perm_rec lin bus does not follow txdl within 40 s; transmitter is disabled 3 can_rxd_perm_rec rxdc has not followed txdc for 4 times; transmitter is disabled 2 can_perm_rec can has not followed txdc for 4 times; transmitter is disabled 1 can_perm_dom can bus is dominant for t > 700 s 0 can_txd_perm_dom txdc pin is dominant for t > 700 s; transmitter is disabled table 138. status register 2, bits (continued) bit name comment information storage table 139. status register 3: command and data bytes command byte 1 st data byte 2 nd data byte read/write address bit <15:8> bit <7:0> x x 0 1 0 0 1 1 data, 8bit data, 8 bit table 140. control register 3, data bytes 1 st data byte <15:8> 2 nd data byte <7:0> function tsd1 tw device_state_1 device_state_0 v1_fail v1_restart_2 v1_restart_1 v1_restart_0 wd_fail_3 wd_fail_2 wd_fail_1 wd_fail_0 forced_sleep_wd forced_sleep_tsd2_shtv1 wd_timer_state_1 wd_timer_state_0 group diagnosis 5 diagnosis 6 table 141. status register 3, bits bit name comment information storage 15 tsd1 thermal warning / shutdown1 occurred since last readout bit is latched until a ?read and clear access? 14 tw L99PM72PXP st spi doc id 023553 rev 3 121/128 13 device_state state from which the device woke up bit is latched until a ?read and clear access? after a ?read and clear access?, the device state is updated. after a wake up, device state is: 01: v 1_standby or 10: v bat_standby 12 device state_2 device state_1 state from which the device woke up 00active 01v 1_standby 10v bat_standby 11flash 11 v1_fail v 1 fail (v 1 < 2 v for t > 2 s) event occurred since last read out bit is latched until a ?read and clear access? 10 v1_restart_2 number of tsd2 events which caused a restart of v 1 regulator (7 tsd2 events forces the device into v bat_standby ) bits are not clearable; is cleared automatically if no additional tsd2 event occurs within 1min. 9 v1_restart_1 8 v1_restart_0 7 wd_fail_3 number of missing watchdog triggers (15 missing watchdog trigger forces the device into v bat_standby ) bits are not clearable; is cleared with a proper watchdog trigger 6 wd_fail_2 5 wd_fail_1 4 wd_fail_0 3 forced_sleep_wd device was forced to v bat_standby mode because of multiple watchdog errors bits are latched until a read and clear access 2 forced_sleep_ tsd2_shtv 1 device was forced to v bat_standby or multiple thermal shutdown events or a short on v 1 during startup. 1 wd_timer_state_1 status of watchdog coun ter of selected watchdog timing bits are not clearable 0 wd_timer_state_0 wd_timer_state _1 wd_timer_state _0 counter 0 0 0 ? 33% 0 1 33 ? 66% 1 1 66 ? 100% table 141. status register 3, bits (continued) bit name comment information storage st spi L99PM72PXP 122/128 doc id 023553 rev 3 6.2.26 status register 4 table 142. status register 4: command and data bytes command byte 1 st data byte 2 nd data byte read/write address bit <15:8> bit <7:0> x x 0 1 0 1 0 0 data, 8bit data, 8 bit table 143. control register 4, data bytes 1 st data byte <15:8> 2 nd data byte <7:0> function swrd_15 swrd_14 swrd_13 swrd_12 swrd_11 swrd_10 swrd_9 swrd_8 swrd_7 sys_err tx_ sync can_to wup wuf can_ silent fd_err group diagnosis 5 diagnosis 6 table 144. status register 4, bits bit name comment information storage 15 swrd_15 status flag for read operation to selective wakeup relevant registers 0: read not done 1: read done see also section 2.10: serial peripheral interface (st spi standard 3.0) automatically cleared by a write 14 swrd_14 13 swrd_13 12 swrd_12 11 swrd_11 10 swrd_10 9 swrd_9 8 swrd_8 7 swrd_7 6 sys_err this bit is a logical or combination of not(swrd_x) or osc_fail or fd_err the selective wake feature cannot be enabled (sw_en = 1) if sys_err = 1 in case of a sys_err the se lective wake-up feature is disabled (sw_en = 0) live bit be updated while the change of swrd_x, osc_fail and fd_err. if swrd_x are all 1, osc_fail is 0 and fd_err is 0, this bit is 0, otherwise this bit is 1. 5 tx_sync status flag for synchronous reference oscillator of the transceiver. indicates that t he last received frame was decoded correctly 0: not synchron 1: synchron live bit updated after each sent can frame L99PM72PXP st spi doc id 023553 rev 3 123/128 4can_to can timeout, bit is set if there is no communication on the bus for longer than t silence v bat_standby mode: can_to indicates that there was a transition from pn_trx_selective_sleep to trx_sleep during trx_stby mode (c an_act = 0, active mode and v 1_standby mode) this bit indicates a can communication timeout. an interrupt on rxdc/nint is generated in this case. bit is latched until a read and clear access 3 wup wake up flag for remote wake up pattern bit is latched until a read and clear access 2 wuf wake up flag for remote wake up frame bit is latched until a read and clear access 1 can_silent online monitoring bit to see if there is silence on the bus for longer than t silence . this flag shows the actual status of the can bus (activity/silence). a microcontroller in stop mode may check this flag periodically auto cleared and set 0fd_err frame detect error. this bit is set at overflow of the frame error counter (fecnt) in sr5 in case of a frame detect error, the device will wake up from pn_trx_selective_sleep bit is latched until a read and clear access table 144. status register 4, bits (continued) bit name comment information storage st spi L99PM72PXP 124/128 doc id 023553 rev 3 6.2.27 status register 5 table 145. status register 5: command and data bytes command byte 1 st data byte 2 nd data byte read/write address bit <15:8> bit <7:0> x x 0 1 0 1 0 1 data, 8bit data, 8 bit table 146. control register 5, data bytes 1 st data byte <15:8> 2 nd data byte <7:0> function reserved fecnt_4 fecnt_3 fecnt_2 fecnt_1 fecnt_0 osc_fail reserved osc_mon osc_mon osc_mon osc_mon osc_mon group diagnosis 5 diagnosis 6 table 147. status register 5, bits bit name comment information storage 15 reserved must be kept at default 14 reserved 13 reserved 12 fecnt_4 frame detect error counter this counter is in creased by 1 in case a frame was not received/decoded correctly (crc error, stuff-bit error, form error). the counter is decreased by 1 with every frame which is decoded correctly if fecnt = 31, the next erroneous frame will wake- up the device, set fderr = 1 and reset fecntx = 0 live bit updated after each sent can frame 11 fecnt_3 10 fecnt_2 9 fecnt_1 8 fecnt_0 7 osc_fail osc failure flag (used device internally) bit is latched until a read and clear access 6reserved must be kept at default 5reserved 4 - 0 osc_mon monitoring of internal oscillator (used internally) live bit updated after each sent can frame L99PM72PXP package information doc id 023553 rev 3 125/128 7 package information 7.1 ecopack ? in order to meet environmental requirements, st offers these devices in different grades of ecopack ? packages, depending on their level of environmental compliance. ecopack ? specifications, grade definitions and product status are available at: www.st.com . ecopack ? is an st trademark. 7.2 powersso-36 mechanical data figure 44. powersso-36 package dimensions a g00066v1 package information L99PM72PXP 126/128 doc id 023553 rev 3 table 148. powersso-36 mechanical data symbol millimeters min. typ. max. a- -2.45 a2 2.15 - 2.35 a1 0 - 0.1 b 0.18 - 0.36 c 0.23 - 0.32 d 10.10 - 10.50 e7.4 - 7.6 e-0.5- e3 - 8.5 - f-2.3- g- -0.1 g1 - - 0.06 h 10.1 - 10.5 h- -0.4 k0-8 l 0.55 - 0.85 m-4.3- n - - 10 deg o-1.2- q-0.8- s-2.9- t - 3.65 - u-1.0- x4.1 - 4.7 y6.5 - 7.1 L99PM72PXP revision history doc id 023553 rev 3 127/128 8 revision history table 149. document revision history date revision changes 16-nov-2012 1 initial release. 01-feb-2013 2 updated section 2.2.2: flash mode and section : wake up from trx_sleep table 32: lin transmitter and receiver: pin lin : ?c lin : added row table 33: lin transceiver timing ? d2, d4: updated test condition table 123: control register 16, data bytes : ? sample_0, sample_1, sample_2: updated default values table 147: status register 5, bits : ? osc_fail: updated information storage 19-sep-2013 3 updated disclaimer. L99PM72PXP 128/128 doc id 023553 rev 3 please read carefully: information in this document is provided solely in connection with st products. stmicroelectronics nv and its subsidiaries (?st ?) reserve the right to make changes, corrections, modifications or improvements, to this document, and the products and services described he rein at any time, without notice. all st products are sold pursuant to st?s terms and conditions of sale. purchasers are solely responsible for the choice, selection and use of the st products and services described herein, and st as sumes no liability whatsoever relating to the choice, selection or use of the st products and services described herein. no license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted under this document. i f any part of this document refers to any third party products or services it shall not be deemed a license grant by st for the use of such third party products or services, or any intellectual property contained therein or considered as a warranty covering the use in any manner whatsoev er of such third party products or services or any intellectual property contained therein. unless otherwise set forth in st?s terms and conditions of sale st disclaims any express or implied warranty with respect to the use and/or sale of st products including without limitation implied warranties of merchantability, fitness for a particul ar purpose (and their equivalents under the laws of any jurisdiction), or infringement of any patent, copyright or other intellectual property right. st products are not designed or authorized for use in: (a) safety critical applications such as life supporting, active implanted devices or systems with product functional safety requirements; (b) aeronautic applications; (c) automotive applications or environments, and/or (d) aerospace applications or environments. where st products are not designed for such use, the purchaser shall use products at purchaser?s sole risk, even if st has been informed in writing of such usage, unless a product is expressly designated by st as being intended for ? automotive, automotive safe ty or medical? industry domains according to st product design specifications. products formally escc, qml or jan qualified are deemed suitable for use in aerospace by the corresponding governmental agency. resale of st products with provisions different from the statements and/or technical features set forth in this document shall immediately void any warranty granted by st for the st product or service described herein and shall not create or extend in any manner whatsoev er, any liability of st. st and the st logo are trademarks or registered trademarks of st in various countries. information in this document supersedes and replaces all information previously supplied. the st logo is a registered trademark of stmicroelectronics. all other names are the property of their respective owners. ? 2013 stmicroelectronics - all rights reserved stmicroelectronics group of companies australia - belgium - brazil - canada - china - czech republic - finland - france - germany - hong kong - india - israel - ital y - japan - malaysia - malta - morocco - philippines - singapore - spain - sweden - switzerland - united kingdom - united states of america www.st.com |
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